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Altera_Forum
Honored Contributor I
1,830 Views

Nios II and Cyclone II confusion

Hi all, 

 

I am doing a FPGA project on DE1 board. May I know whether DE1 has Nios II processor? I read a lot of documentation about Nios II but still confuse between Cyclone II and Nios II. I know DE1 board has Cyclone in it but what about Nios? I am very confuse. Please help. Thank you in advance.
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8 Replies
Altera_Forum
Honored Contributor I
69 Views

Cyclone II is the FPGA a pice of hardware 

Nios II is the embedded softcore processor, thats "software" 

if you create a design with nios II then you can almost easily port that design to almost any altera fpga 

 

if you look at opencores.org, you will find a couple of well known softcores like z80 or 8051, they also run on your de1
Altera_Forum
Honored Contributor I
69 Views

Thanks a lot. That clear up all my confusion. I thought Nios II is hardware. Now I going to implement my handwritten recognitions in DE1. Thanks again.

Altera_Forum
Honored Contributor I
69 Views

Few more questions,  

 

Nios II can be programmed using C/C++ right ? 

 

You said that any design using Nios can be port into any FPGA. Does that mean I can mix my design using C/C++ in Nios and Verilog/VHDl modules in my project?
Altera_Forum
Honored Contributor I
69 Views

sorry for confusing you 

nios executes C/C++  

but nios itself if coded in some kind of hdl as other functionality is done in vhdl or verilog hdl or schematic entry 

 

if you have an altera fpga that has a nios ond some other functionality then you can swap to almost any other altera fpga. for example you need a bigger fpga or a faster one ... 

 

C/C++ is your application that is executet by the nios cpu. 

 

and to completly confuse you, some parts of you application can accelerated by the c to hardware functionality to speed up the stuff.
Altera_Forum
Honored Contributor I
69 Views

 

--- Quote Start ---  

sorry for confusing you 

nios executes C/C++  

but nios itself if coded in some kind of hdl as other functionality is done in vhdl or verilog hdl or schematic entry 

 

if you have an altera fpga that has a nios ond some other functionality then you can swap to almost any other altera fpga. for example you need a bigger fpga or a faster one ... 

 

C/C++ is your application that is executet by the nios cpu. 

 

and to completly confuse you, some parts of you application can accelerated by the c to hardware functionality to speed up the stuff. 

--- Quote End ---  

 

 

 

Thank you for replying. From what you posted and I read from altera website, now I understand Nios is a "softcore" CPU like system. After reading the Nios II software development document, I have some thoughts which need to be confirmed: 

 

Your post also said Nios execute C/C++ application. So, does that means I can write any appplications in C/C++ (eg. image binarization or filtering) to be executed by my Nios design? Or the Nios CPU can only execute some specific C/C++ applications only? Assuming I had designed my Nios CPU. 

 

Sorry for keep asking. I had read a lot of documentations and being a beginner, hope you do not mind and forgive me for being a bit stupid. 

 

Thank you in advance.
Altera_Forum
Honored Contributor I
69 Views

this forum is ment to be a place for asking questions and help each other, so keep on asking :-) 

 

with a fpga you are free to do things very easily and fast. if you need a "task" to be done very fast, implement it in hardware (HDL) you can split jobs where some parts are pure software and others are hardware executed.  

one example is the often used crc function. imagine a crc done purely in software and yopu need to calculate the crc over 1 MByte. that would take a lot of clock cycles. imagine this job done as pure hardware that is trimmed only for that but does this very fast. now your c/c++ application is coded around your hardware crc. you can create your own crc hw accelerated function as a ip block where you have the crc register and the data register. but nios also enables you to create custum instructions where your crc is calculated with only one clock cycle per data 

you could implement a fft functionality in hardware and let your c/c++ application fetch input data from ethernet, and send the fft out data back via ethernet.  

if you think about video processing, store frames with you c/c++ application and let the image processing be done by a custom hardware function where this ip does the image data fetch automatically sent the data from processing block to processing block and at the end store it to the desitination memory. 

hope you get the idea of mixing hardware and software
Altera_Forum
Honored Contributor I
69 Views

Thank you. That clears up a lot of my confusion.

Altera_Forum
Honored Contributor I
69 Views

Hi again,  

 

I dont want to open multi thread to ask this question. May I know whether I can do simulation of my software application in Nios IDE without downloading it into FPGA board ? I read in the "Using the Nios II Software Build Tools" from altera website said that I need to download it into FPGA. I had searched this forum regarding this but to no avail. Thank you in advance.
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