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AShiv
Novice
1,110 Views

Nios II on the De0-Nano-SoC

I am wondering if it is possible to use just the Nios II and FPGA portion on this board, aka without HPS. So, that the Nios II doesn't need to use the HPS bridges to access the DDR3. I know it makes this board kind of silly, since I would not be using the HPS, but I am just using it to test some idea. I am trying to get the Nios to take some data out of the DDR3 and using the NicheStack to send UDP packets. If anyone has any tips i'd appreciate it.

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5 Replies
AnandRaj_S_Intel
Employee
155 Views

Hi,

 

DDR3 devices connected to the HPS and its signals are connected to the dedicated Hard Memory Controller

for HPS I/O banks.

Hence HPS is must required to access the DDR3.

 

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

Abe
Valued Contributor II
155 Views

The DDR3 memory on the DE0-Nano is only accessible using the HPS since the DDR memory pins are directly routed/connected to the HPS I/O in the board.

 

Why not try using onchip RAM for NIOS-II? What is your memory requirement for processing the UDP packets? Can it be done using on-chip memory?

Daixiwen
New Contributor I
155 Views

Technically I think you could use the FPGA to sdram bridge to connect the Nios II CPU to the DDR3, but you will still need to run the preloader on the HPS to calibrate the DDR3 and enable the bridge.

AShiv
Novice
155 Views

Thanks for all the help everyone, I figured that was the case. Essentially in my final design, I don't intend to use a board with an HPS, since I'm not planning on using it. The amount of data I am storing on the FPGA is too big for the on chip memory of 64KB. I've connected the FPGA to the DDR3 via the F2SDRAM bridge, but I am having trouble getting the NIOS to connect to it, I am not really sure how to handle the addressing issues of connecting the data and instruction masters to the SDRAM bridge. Does anyone know of any examples of how to get this to work?

Daixiwen
New Contributor I
155 Views

It's a rather unusual design so I'm not sure you'll find examples of this. Basically you should connect both masters to the F2SDRAM, at the same address. The address itself is not that important. You will also need to make sure you updated and recompiled the preloader for the HPS, and that you run it to enable the bridge. (AFAIK the bridge is enabled in the preloader). Don't put anything on the HPS's flash or the HPS CPU will attempt to boot on it and copy its software to the SDRAM, interfering with your application.

For the NIOS what I'd do first is to include a 64ko on chip memory, also connected to both masters, and use it as main memory at first. Try to run a memory test program from there, that would read and write in the SDRAM. If it works, then try and put your program there.

If it doesn't work, put some signaltamp probes on the F2SDRAM slave interface to find out where it is stuck and what the CPU is trying to do.

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