ODDR clock

[ymiler]

Hi,

I need to create a source synchronous connection between two FPGAs.

FPGA A needs to transmit 32 data bits with a clock to FPGA B.

All 32 bits are sampled by a PLL clock and then sent to 32 IO_OBUF pins. The same PLL clock (which samples the 32 data bits) is connected to another IO_OBUF.

I would like to align the clock and the 32 data bits to the same flip-flop delay value.

Is there an IP core or an alternative method to create an ODDR that is sampled by the PLL clock and generates a new clock that is aligned with the flip-flop for the 32 data bits?

Thank you!

[AqidAyman_Intel]

We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum cases, along with others, did not get through as intended. As a result, we have a backlog of cases that we are currently working through one by one.

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Thank you for your understanding.

[AqidAyman_Intel]

Hello,

It seems like a Double Data Rate I/O IP. I share you the link to the IP user guide:

https://www.intel.com/content/www/us/en/docs/programmable/683148/17-0/double-data-rate-i-o-altddio-in-and-54289.html

Regards,

Aqid

[ymiler]

My device is Stratix 10,

My Quartus version is Quartus Prime Pro Edition 22.3

I don't find ALTDDIO IP in this version, maybe there is other IP which relevant to my version / device? 

[FvM]

Hi,
in Quartus Pro, ODDR and IDDR functions are contained in GPIO Intel IP.

[ymiler]

OK ,

I have several Q 

1)Currently , my SDC file include definition of the PLL clock and input & output delay to the data output ports

Should I change the constraints since I add GPIO IP which get the PLL clock as input ?

2)Should I expect better result with the GPIO IP ?

[FvM · Accepted solution]

Hi,
there's probably no advantage by using GPIO. A behavioral or structural description of the output logic will most likely end up in a similar or identical hardware implementation. I mentioned GPIO because you asked.

Also your existing SDC specification should work.

[AqidAyman_Intel]

I wish to follow up. Do you have more questions or support needed?

[ymiler]

No

Thank you