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Altera_Forum
Honored Contributor I
905 Views

Off Chip Memory Issue (DSP Dev board)

Hi, 

 

I'm having a bizarre issue with the DSP development board (Stratix II S180) and wanted to get some opinions on it. I use the SRAM and sometimes when I compile the project it will work just fine other times it will spit out junk data. 

 

Here is what I have gathered: 

1. If the read address (any) is tied to a single value it will always produce the correct memory value for that address. Indicating it is not an issue with write. 

 

2. If the read address ever changes it will never produce the correct memory value. Even during consecutive read commands. 

 

3. When it does return a junk value it has many consistent bits. 

 

4. The issue is more common with larger designs. I.E. just running the memory controller works just fine. 

 

Any thoughts would certainly be appreciated, this is driving me up the wall. 

 

Thanks, 

Nathan
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3 Replies
Altera_Forum
Honored Contributor I
52 Views

Does your design meet all timing requirements? It looks like a timing issue to me.

Altera_Forum
Honored Contributor I
52 Views

Thanks for the input. 

 

My first thought was a timing issue of some sorts. However, I can send a read command for 10 consecutive cycles (i.e. same address and control bits held for ten cycles) and it still behaves the same way. It is a low speed design (70 MHz) so this should meet all timing requirements by a large margin.
Altera_Forum
Honored Contributor I
52 Views

This shows that when your signals are stable on a longer period than one read cycle, everything is fine. Timing issues can be an explanation for that. 

Could you put some Signaltap probes on the signals and see what's happening?
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