FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits

On die capacitance

SHash6
Beginner
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Currently, I design the power distribution network for my customer. My customer uses intel stratix 10 mx. Then, I made some evaluation boards and measure some performance. As a results, the voltage fluctuation exceeds the limit. It's come from the anti-resonance peak of the PDN impedance. So I have to re-design the PDN. Could you tell me the on die capacitance of stratix 10 mx to decrease and re-design the PDN?

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Rahul_S_Intel1
Employee
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Hi ,        

The on-die capacitance is not published in our documents, requesting you to follow the PDN page no:48 to get the value

 https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_dev_specific_pdn_20.pdf?wapkw=PDN

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