The HPS DDR4 is 1.2-1.5V. Why is the clock driver VDDO 1.8V, and how is the FPGA I/O tolerant of that?
The Si5338 VDDO minimum is 1.5V, which doesn't seem to be compatible with 1.2V DDR4.
On pg 40, U49 VDDO is connected to 1.8V.
CLK_HPSEMI_P/N is the HPS DDR4 clock. This connects to the HPS memory I/O bank 2K on pg 19.
VCCIO for this bank is connected to HILOHPS_VDD on pg 74.
HILOHPS_VDD is generated on pg 62 and can be 1.2V, 1.35V, or 1.5V.
Hi Sir, The reference clock is using LVDS IO standard. Thus, the clock source is 1.8V.
For LVDS input, it is power-up by the VCCPT which is 1.8V. Thus, there are no conflict with the VCCIO.
See this document for the details. Table 33, see note 6.
Input for the SSTL, HSTL, Differential SSTL, Differential HSTL, POD, Differential POD, LVDS, RSDS, Mini-LVDS, LVPECL, HSUL, and Differential HSUL are powered by VCCPT