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Altera_Forum
Honored Contributor I
2,932 Views

PC <-> S530Dev. Bd. Reg R/W interface?

Hi - so I just got my first Altera Development kit (S-IV GX S530). My "hello world" project starts with a tiny user-designed design (i.e. RTL code) that I download to the board that consists of some registers. I want to have a simple PC interface that allows me to read/write these registers on the FPGA on the development board from the PC. It can be a command-line interface (I can later put a GUI on top of it). I'm guessing/hoping that the building blocks for this structure exist and I just have to paste them together. (PC-based USB driver -> USB interface on FPGA, or maybe Rj45 Ethernet?)  

 

Can anyone point me in the right direction? 

 

Much Thanks!  

/j
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33 Replies
Altera_Forum
Honored Contributor I
91 Views

 

--- Quote Start ---  

I'm guessing/hoping that the building blocks for this structure exist and I just have to paste them together. (PC-based USB driver -> USB interface on FPGA, or maybe Rj45 Ethernet?)  

 

Can anyone point me in the right direction? 

 

--- Quote End ---  

The JTAG interface can be used to implement communications. However, you are then limited to using Altera applications on the host. This is not too much of a pain for simple tests, but it does get annoying. I'm looking into a better solution and will post my results. Start by using an Avalon-MM JTAG master along with the SystemConsole Tcl functions to access the device. Design your custom logic as an Avalon-MM slave device. 

 

If you use the RJ45 interface, then you'll need a network interface controller. There is an Altera TSE IP core, but I have yet to test it. I'm not sure how much work it would be to code your own. Once you have the ethernet connected as an Avalon-MM/ST device, then you can code up a server on a NIOS II processor. This would provide a higher-bandwidth interface. 

 

If you have the board plugged into a PCIe motherboard, then you can use a PCIe-to-Avalon-MM bridge IP core, and then communicate from the host as if the board is a PCI device. This is simple under Linux, and you can probably use the Jungo driver under Windows. 

 

I have the same kit as you, but with the 230 devices. I've been using JTAG for testing up until now, but the ethernet and PCIe tests are on my TODO list. If you get stuck, ask, and I'll help if I can. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
91 Views

Hi Dave - that's a start - thanks!. Can higher level applications (like LabView) talk to the Altera application on the host? 

/j
Altera_Forum
Honored Contributor I
91 Views

Also - something about your explanation confuses me. I think you're telling me to put the Avalon-MM JTAG Master device on the FPGA as a piece of IP, and design my logic as an Avalon slave. So far so good, but I don't quite understand the path from the JTAG Master IP on the FPGA to the PC - will it "bind" to the JTAG port automatically? What SW App do I run on the PC to get a command-line interface to it?  

 

If there's like, a good tutorial on this (or a few manual section), I'm game to RTFM. 

 

Thanks very much! 

/j
Altera_Forum
Honored Contributor I
91 Views

 

--- Quote Start ---  

Can higher level applications (like LabView) talk to the Altera application on the host? 

 

--- Quote End ---  

Not without a little extra work. 

 

There are effectively two separate methods to create JTAG interfaces; low-level access via the Virtual JTAG IP core, and access via SOPC Builder components such as the JTAG to Avalon-MM master bridge. Both of these IP components come with a corresponding set of Tcl procedures. 

 

The Tcl procedures access the JTAG interface via DLLs with unpublished APIs. There are posts explaining how to use some of these directly, but I have not tried this. 

 

I've used both the Virtual JTAG and Avalon-MM IP cores. I'd recommend playing with the Avalon-MM IP first. Using Qsys or SOPC Builder, create a system with a JTAG to Avalon-MM master, a RAM block, and a GPIO block, and use SystemConsole Tcl commands to access this system. 

 

I recall a fairly decent webinar on the topic ... perhaps it was one of these 

 

http://www.altera.com/support/examples/on-chip-debugging/on-chip-debugging.html 

 

Have a look at that stuff, and if it becomes too confusing, I'll create a design and some scripts for you to play with. 

 

Back, to your original question; Labview cannot talk to any of these IP cores directly, since the access is via a console in an Altera application. However, you can write a Tcl server, start that using the appropriate quartus command-line tool and then use sockets from Labview. Not ideal, but not too ugly either. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
91 Views

 

--- Quote Start ---  

I don't quite understand the path from the JTAG Master IP on the FPGA to the PC - will it "bind" to the JTAG port automatically? What SW App do I run on the PC to get a command-line interface to it?  

 

If there's like, a good tutorial on this (or a few manual section), I'm game to  

--- Quote End ---  

 

 

Its all about knowing the right terminology, eh. Look in the Quartus Handbook at System Console. This tool is a Tcl console with Tcl procedures that can be used to find your device on the JTAG chain, and then send read/write commands. The Virtual JTAG interface is accessed from a different tool, quartus_stp, with different Tcl procedures. Start with System Console, as this seems like the tool Altera wants you to use. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
91 Views

Hi Dave - a lot to chew on here - I'll be back after digestion is complete 8-} 

 

Thanks VERY much 

/j
Altera_Forum
Honored Contributor I
91 Views

Hmmm - so many choices. It seems like i could get pretty far with In-System Sources and Probes (i.e., peek and poke), and this has the advantage of being "lighter" than system console (and defers the rampup on Qsys/sw driver stuff, etc), but it does sound like it eventually runs out of steam and I'll want to switch to System Console (and the more-SW-like paradigm, as well as Qsys). So I'm wondering how much wasted effort there is in starting with ISSP as it will get me up and running quicker..... 

/j
Altera_Forum
Honored Contributor I
91 Views

 

--- Quote Start ---  

So I'm wondering how much wasted effort there is in starting with ISSP as it will get me up and running quicker..... 

 

--- Quote End ---  

The System Console approach is not too bad. Rather than doing a lot of reading, start with 'doing'. Create a Quartus project, select the Stratix IV part, start Qsys, create a new Qsys design, add the JTAG Avalon-MM master, the RAM, and the PIO component. Put the LED at address 0, and the RAM at say address 0x1000. Instantiate the system in a top-level VHDL or Verilog design. Synthesize it. Assuming your PIO has 8-bits, go into the pin assignments editor and assign these pins to the LEDs on the board. Re-synthesize the design; check the .pin file to confirm that only the LED pins are used and the others are reserved (tri-stated). 

 

Start system console, eg., in Quartus v11.0 Tools->Transceiver Toolkit, and then type 'source {<windows path to>/jtag_cmds.tcl}', where the curly braces pass the path to the 'source' command as a Tcl list. Look at the jtag_cmds.tcl file to see the procedures in there (the .tcl file is in the .zip attachment). 

 

Now type 'jtag_read_32 0' to read the LEDs, 'jtag_write_32 0 0x55' to write to them, or 'jtag_read_32 0x1000' and 'jtag_write_32 0x1000 0x12345678' 

to access the RAM. There are also LED Tcl procedures defined, eg. led_read and led_write 0x55. 

 

That should give you enough of an incentive to go this route :) 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
91 Views

good advice, and I think the right path to take. But you forgot step 0 - "learn enough about Qsys to use it" which is where I need to start 8-}.  

 

Thanks for all your help. I may have to focus elsewhere for the next day or two but will be back on this next week. 

 

best 

/j
Altera_Forum
Honored Contributor I
91 Views

 

--- Quote Start ---  

But you forgot step 0 - "learn enough about Qsys to use it" which is where I need to start 8-}.  

 

--- Quote End ---  

 

 

I didn't want to spoil the fun part ... 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
91 Views

8-}  

 

(lengthening to > 10 char)
Altera_Forum
Honored Contributor I
91 Views

hi! 

it seems that i have a similar problem like yours.  

i wanna read and write register of my nios system by using the jtag to avalon master bridge by using system-console.  

 

i can do it by using the system-console.exe. 

my problem is, that i wanna use the new (quartus 2 11.0) Matlabapi to do this.  

wombat - altera guru - also gave me some hints how i can do it (last page http://www.alteraforum.com/forum/showthread.php?t=28699). but i get the error: 

 

Could not initialize class com.altera.systemconsole.internal.plugin.jtag.aji.AJICable 

 

it seems like a problem with the jtagdni.dll but i don´t know how i can fix it. 

perhaps you can give me an idea how to fix it ...  

 

greets
Altera_Forum
Honored Contributor I
91 Views

basti-b - I would post this in a new thread - you'll get greater visiblity. thanks! 

/j
Altera_Forum
Honored Contributor I
91 Views

Hi Dave - it's been a busy few days. 

I got my board up, ran all the system tests. did the Qsys example, downloaded to the board, and saw that working. Played with System Console and the 'dashboard'. And now I'm trying to push my own project through the process. What I'm finding is a disconnect between Qsys and Quartus. I mean, after I have a project complete in Qsys, how do I get it into an FPGA? Do I set up the project, pinout, etc, manually, or is there some Qsys-> Quartus tool that helps. I'd be surprised if there wasn't, but I'm not finding it. I appear to have to generate project file, sdc file, etc, from scratch. Really? 

 

Thanks! 

/j
Altera_Forum
Honored Contributor I
91 Views

 

--- Quote Start ---  

 

What I'm finding is a disconnect between Qsys and Quartus. I mean, after I have a project complete in Qsys, how do I get it into an FPGA? Do I set up the project, pinout, etc, manually, or is there some Qsys-> Quartus tool that helps. I'd be surprised if there wasn't, but I'm not finding it. I appear to have to generate project file, sdc file, etc, from scratch. Really? 

 

--- Quote End ---  

Qsys generates a component. There's nothing special about that component, it just happens to be automatically generated. 

 

An FPGA design consists of a pinout, SDC file, and HDL files; one or more of which may be Qsys generated components. 

 

I typically generate top-level designs using; 

* a generic top-level design entity (VHDL) containing all pins on the board 

* a pin assignments Tcl script that sets up all the I/O 

* SDC files 

* A design-specific Tcl script that ties it all together (runs the Quartus build) 

 

The top-level entity/architecture file is copied-and-pasted into each design, and then the architecture body is edited to connect the design-specific top-level design into the generic top-level design (which always has the same pin names). For example, lets say I have a Qsys component called qsys_test that I want to simply drop into the FPGA. I would take my Stratix IV GX development kit top-level design s4gxdk.vhd and inside that file instantiate u1 as the qsys_test component, then connect up whatever pins I need, eg., connect a qsys_test bus called pio(7 downto 0) to the LEDs or a GPIO bus in the top-level generic design. 

 

So, there is a little manual work required, but its similar between designs, so most of it can use common scripts (to minimize copying files), or a common template that can be copied-and-pasted, followed by minor editing. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
91 Views

Thanks Dave - I assume the scripts you refer to are your own. I admit I'm dealing with it by starting with the .qsf from the development kit and working from there. The examples/tutorials gloss over the top-level build so I was hopeful there was some magic there 8-} 

thanks! 

/j
Altera_Forum
Honored Contributor I
91 Views

Hi Dave - I'm getting close to banging my head against the wall now. but see the next posting.. 

/j
Altera_Forum
Honored Contributor I
91 Views

So let me be more specific: I have assembled a project in Qsys consisting of a Clock source, a JTAG-to-Avalon Master Bridge, and a custom Avalon Slave which is no more than a register file. I used Qsys to connect the reset network*, and generate all the files, and instantiated the top-level file from Qsys as my top-level project file. There are only 2 inputs (clk, reset_n), for which I correctly connected pins (based on the example project for my FPGA board). I also constrained the clock, and used the my_constraints from the example project to constrain the JTAG interface. I then built it. The warning count was very low and the warnings seemed reasonable. I then programmed the board. (with the rotary switch on "0"). I then brought up system console.  

 

These commands work 

 

set mm [lindex [get service paths master] 0] 

open_service master $mm 

is_service_open master $mm // returns 1 

 

However - any other commands, like 

 

jtag_debug_sample_clock $mm 

 

jtag_debug_sample_reset $mm 

 

jtag_debug_loop $mm <number> 

 

jtag_debug_sense_clock $mm 

 

or, the one I want 

master_write_32 $mm 0x0 0x1 

 

All produce a message "channel closed". The jtag sense/sample commands all return "0", and the jtag_debug_loop returns "error: java.lang.NullPointerException while executing <cmd>".  

 

The master_write_32 returns "error: java.lang.RuntimeException: Channel closed while executing <cmd>'"  

 

I feel like I'm awfully close here, and just haven't tagged second. What does "Channel closed" mean???? 

 

Thanks! 

/j 

 

*I really think Qsys didn't do the reset network right - it tied everything to everything. So I tried it again with a daisy chain - clk source -> JTAG/Avalon Master -> my Slave. didn't make a different but this seems more correct.
Altera_Forum
Honored Contributor I
91 Views

Its quite possible you have a design error. 

 

Did you try running the design in Modelsim first? 

 

The Verification IP suite contains an Avalon-MM Master BFM that can be added to your Qsys design. You can use that component to generate Avalon-MM master read/write transactions.  

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
11 Views

That's my next step, I wish I knew what the error meant though. 

 

Dave - let me ask you something. All I'm really interested in is adding the JTAG-To-avalon-master to my designs. Now that I've been through Qsys, and, as you say, Qsys is just a way to generate RTL, do I really need all the overhead? Why can't I just create my own RTL with a call to the JTAG-To-avalon-master, + my code, and use a QIP file so Quartus can find the avalon component. It seems much easier... 

 

Thanks! 

/j
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