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Honored Contributor I

PCI Express Dev. Board (Stratix II GX) with Core problems

Hi there! 


I am having big trouble getting a design to run that contains a PCI Express Compiler Variation only. 


PCIE Parameters are: 

- Native Endpoint 

- 1.1 

- x8 

- Avalon-ST Interface (64bit) 

- PCI Express Compiler 9.0 


I am using Quartus II 9.0 SP1. 


I create the variation and hook up all inputs (npor, rstn, etc.) as in the DMA example that is created with the variation. 


I can see that the design is running (core generates 250 MHz clock and design toggles "alive LED"), but nevertheless no PCIe link is established. 


The factory design inside the embedded flash memory is loaded on start-up and works. When I say works, I mean that the provided App is able to send and receive DMA requests... 


When I program the FPGA while the OS is up, the application stops with the error message "DMA still pending". 


When I flash while the BIOS is performing the POST etc. the system hangs and won't start. 


The board is shipped with at least 6 different designs (QAR-format).  

How can I know which is the one stored in the flash? 


Does anyone have solved a similar problem or does have a very, very basic working project? 


All I want to do right now is ensure that the core receives TLPs in a deterministic way. I have a driver and can send TLPs whenever I want. I just wanted to check the rx_st_sop signal to know wether a TLP has been received by the core. 


Please help me, because I have run out of ideas what could be wrong... :( 


Big thanks! 


EDIT: The example "chaining dma" works as far as I am able to read the config space. With the minimal design I built, lspci recognizes the Config Space as "unknown header type" 7f...
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3 Replies
Honored Contributor I



I have exactly the same problem. If I load the design after BIOS and OS startup, I just do a pci bus rescan ( easy under linux ) and it's working fine.  

BUT, If I reboot the pc with my design loaded into devboard, the bios hangs forever, and nothings happens. 


I don't understand why. The Altera reference designs work fine, but not mine.  


What could be a reason for that ?  

Did you find the solution ?  



Honored Contributor I

Well, several problems might be involved. 


To have a working instantiation of the PCIe Core I needed to connect one of the test signals. 


Then with a self-written driver I was able to send data to the card & the rx_st_sop signal would indicate reception of data. 




I just looked up the signal. The name is test_in and I had to apply this: 


test_in(4 downto 0) <= std_logic_vector'("01000"); 


Also ensure that you reset according to the specified reset_times, 16/1024 cycles IIRC. 


Regarding the configuration problem: 


In case you want to have your design loaded before BIOS does the PCI initialization you will have to load it to the flash.  

This can be done with urJTAG for example or you can go the Altera way. 


But I have not done too much with the PCIe core since we moved away from it. 


Hope that helped a little. 




Honored Contributor I

Yep...The configuration works can go complicated sometimes and drive you crazy