Hi,I'm trying to develop a PCIx Interface with the Cyclone IV EP4CGX15BF14C6. My PCI-E is generated by SOPC, followed the step, which shown in "An SOPC Builder PCI Express Design with GUI Interface". But after I download my sof file, the development board is not detected in PCIx list in windows. The document use Stratix Device. Is there any differente between Cyclone and Stratix when generate PCI-E ip using SOPC? also there are so many pins floating out in the top.v file. I only set the following pins in my qsf file, set_location_assignment PIN_J2 -to rx_in0_pcie_compiler_0 set_location_assignment PIN_G2 -to tx_out0_pcie_compiler_0 set_location_assignment PIN_A10 -to pcie_rstn_pcie_compiler_0 set_location_assignment PIN_D10 -to reset_n set_location_assignment PIN_J6 -to refclk_pcie_compiler_0 for other pins, i don't know which pins i need to set to VIRTRUL pin, which pins i need to assign to the real pin. I need you help urgently. Thanks, Tomato
Have you checked the high performance design?https://www.altera.com/servlets/download2?swcode=www_ref-pcie-hp-c4gx&referer=https://www.altera.com... At least, you should be able to understand which pin should be assigned. Apparently, 5 pins are not enough.
thanks for your reply.I have download the example. In this example, the PCIe is generated by PCIe complier in MegaWizard. this PCIe use ST interface. But I want generated PCIe by SOPC, which use MM interface. Is there an example project in which PCIe IP is generated by SOPC and using deviece Cyclone IV EP4CGX15BF14C6.
I'm in the same boat (however using a different dev kit). Referring to the high performance PCIe implementation isn't really all that helpful due to the substantial differences between the SOPC generated system and it.Is there any complete (preferably minimal) PCIe reference design using the SOPC flow? Thanks Tommy
Thanks slacker,I took a look at that, but it's a little overwhelming and I'm not sure I would have more luck with that than I do with the example from Chapter 16 of the PCI Express Compiler user guide. I followed the example in Chapter 16 to the letter (though the text is inconsistent with Figure 16-3, I tried both ways). Sadly, the resulting design doesn't work. Following other suggestions here, I added the altgx_reconfig block, but to no avail. (Lots of other things tried in vain). I'm sure it's something basic I'm missing, so I'd really love to see this example completed for the Arria II GX dev kit.
@totototomato Which version of Quartus you are using ? I strongly recommend 10.1. I have a PCIe design for the DB4CGX board compiled with 10.1 which runs without problems. Quartus 10.0 caused problems.
Hi,i have exactly the same problem using Quartus 10.1 with a Stratix IV GX EP4SGX530KH40. I followed the guide to the letter for the SOPC example. Unfortunately, the PC does not detect the board. I read on an other forum that the problem may be caused by a x4, x8 misunderstanding from the PC. Indeed, my board has a x8 connector and the PC may recognized her as a x8. The example in the guide use a x4 connection. I tried to generate a x8 hard ip with the SOPC builder, but you can't choose a x8 with the SOPC builder. :s BTW: i tried several configurations with the DIP switch but nothing changed.
For what it's worth, I had no trouble instantiating it through the MegaWizzard and theassociated chaining DMA example works fine (ie. shows up in lspci). I've given up on doing this through SOPC builder and is pursuing the excellent modular bridge that Slacker recommended above. Unfortunately it was made for Q II 9.1 and doesn't work that smoothly with the most recent Q II (10.1sp1). I'm not sure where to ask about that. Tommy
HiI am trying to get AN532 PCI-SOPC design working with Arria II GX development kit. But didn't have success after 1 week. It would be great if some one could share some tips or design.