Can anyone say if the Stratix V GX FPGA development board passes the PCISIG compliance tests for Gen3 ? Or has been to a PCISIG "plugfest".I ran the board configured as Gen3 X1 , which worked at Gen 3 in an X86 system , but seemed to be stuck at preset P7 settings when tested on a protocol aware BERT. Any ideas on how to get it to pass the LeCroy EP compliance tests on the PERT ? Thanks, Bob.
This seems to indicate the preset is fixed ...• Stratix V PCIe Hard IP Presets: http://www.altera.com/support/kdb/solutions/rd01232015_198.html My question then is what to do to get the Stratix V Gen3 design to be PCI SIG compliant given it has to negotiate 3 presets to apss the compliance tests. I myst be missing something here
Here is an answer ...http://www.alterawiki.com/wiki/pci_sig_gen3_x8_merged_design_-_stratix_v I came across this in a search I guess .. It is a design with 3 compliance based functions that I assume is the same PFGA design used to pass PCISIG compliance. I have build the design and committed to FLASH and will run the compliance tests on it ... any ideas on how to get to EP loopback mode ? Interestingly the 3 compliance modes are DIP Switch selected .... OR if you only have the FPGA, clocks and power, there is a "probe" function allowing the switch inputs to be forced as if there was a virtual switch ... neat ! Thanks, Bob.