FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5287 Discussions

PCIe Gen1 x1 or x4 example design share

BQi
Beginner
214 Views

we need PCIe Gen1 x1 or x4 example design, it can base CIV GX, C5 GX or C10 GX

but we need the simulation testbench would be include into the reference design. would u pls share us the design.

 

if you do not have. would u pls advice how to do it with C5 GT design(https://www.intel.com/content/dam/www/programmable/us/en/others/support/refdesigns/ip/interface/PCIe...)? how can it support simuluation?

 

would u pls help us port this design into quartus 16.1?

if we check the option (support simulation in qsys)

0 Kudos
3 Replies
BoonT_Intel
Moderator
149 Views

Hi Sir,

For Cyclone 10 PCIe, you can just set to gen1 x1 or x4 accordingly then generate the simulation example design from the GUI directly.

See chapter 2.3. Generating the Design and 2.4. Simulating the Design for details.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avst.pdf#pag...

BQi
Beginner
149 Views
I want C5GX ref design and simulation prj Thanks and Best Regards! Brand Qi / 齐闯 Arrow Electronics Tel: 010-56064176 or 13911556862 Email: brand.qi@arrowasia.com<blocked::blocked::blocked::blocked::blocked::blocked::blocked::mailto:brand.qi@arrowasia.com> Addr: 28/F, Taikang Financial Tower, 38 North Street of East 3rd Ring, Chaoyang District, Beijing
BoonT_Intel
Moderator
149 Views

Hi Sir,

You should state it clearly if you only need the C5GX design. 😉

From your original description, you need either CIV CV or C10. So, I gave you the latest device which is C10.

 

For Cyclone V PCIe, you also can generate the example design

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_c5_pcie_avst.pdf#page...

Section Generating the Testbench and section Simulating the Example Design

 

Reply