Any of you familiar with the PCIe design example for Arria10 to help me with the following?
I generated two PCIe design example for Arria10 SX for two different boards (with different Arria10 SX part numbers) using Quartus pro 18.1. I see the following:
I use signal tap to look into the rx_st and tx_st buses and I see something strange:
I use Avalon ST, PCIe gen2/3 x4, 64 bit, 250Mhz. The design example seems to target the Arria10 GX development board but I think it should work with Arria SX part on my board since there is no error when i compile for Arria10 SX.
I only have the signals for PCIe bus between the FPGA board and the host. I don't have any of those signals that are available for Arria10 GX development board. This should not be a problem, should it?
Let me know if you want to see some of the waveform on rx_st and tx_st bus. I can capture them and share with you.
Thank you for your help.
AN456 does not help. I followed the document in the link below to generate the example design and it failed as I described in the post.
Do you know if it works with Arria10 SX or does it work with Arria10GX only?
Yes, the AN456 and generated example design has tested using A10 GX development kit. I don't see why it can't work for SX device.
What driver you are using? Linux or window? Is this a custom board? I would suggest to add the "ltssm" signal in signaltap to confirm it can get a stable L0, and the "lane_act", and "currentspeed" are all expected.
I use the following board and I see the same problem:
I don't have any Arria10 GX board to try.
As I continue to test the design, I notice something unusual. The same design only works in some PCIe slots of the motherboard even though all the slots on the motherboard are PCIe gen3 x8 or x16.
These are good motherboard and all slots work with other NIC cards.
Are you aware of this issue? Any idea to help? Any suggestions?
I'm not aware of this issue, if possible, need to try to understand the difference between these slots, e.g timing of PERSTn, and also when the refclk is stable.