PCIe hard IP example design generation fail

[CHung]

Hi

I generate example design of Stratix PCIe hard IP and get error message as following figure.

Could you please fix the problem?

PS. I'm using Quartus v18.1.2 and v19.1.

[SengKok_L_Intel]

Hi,

I'm using v19.1 to generate the Avalon-MM intel Startix 10 Hard IP+ example design by using the default setting, but I can't see the same error.

Questions:

1. How do you configure the IP? Does using default settings also having the same issue?
2. What is the OPN (Device's full name)?

Regards -SK

[CHung]

Hi SK,

1. I got the same errors either using default setting or selecting gen3x8 configuration.

2. The device full name is 1SM21CHU1F53E1VG.

Thanks.

[CHung]

Hi,

I've checked again, it's not default setting. Because we are based on a reference design.

Please see the attached setting file.

​I've tried 1SM21CHU1F53E1VG (our current device) and 1SM21BHU1F53E1VG (reference design), they both failed.

Thanks.​

[CHung]

By the way, the reference design is:

https://fpgacloud.intel.com/devstore/platform/19.1.0/Pro/an881-pcie-avmm-dma-gen3x16-ddr4-and-hbm2/

[SengKok_L_Intel]

Hi

This problem may only happen in certain PC or OS. For a quick workaround, I have helped to generate the design and attached it here for your reference.

Regards -SK