We have Arria 10 SOC (SX 066 NF40). There is PCIe hard IP at GXBL1D and GXBL1C.
We like to implement a PCI4 Gen 3 with 4 lanes.
#1
I like to check if any 4 lanes on these bank could be used?
For example, two lanes from GXBL1D and two lanes from GXBL1C.
#2
Was there any restriction for the REFCLK pin location?
Hope to hear from ASAP. Thank you.
