Hello, I'm sorry to ask you such simple things, but I'm nearly running mad.My Problem is: I want to check the data of a 32 bit wide general bus. This bus has a clock of 50 MHz. My intention is to use the Arria II GX Development Kit to capture the Data into the memory and read them into my Computer via PCIe. I think I can expand the "PCI Express to External Memory Reference Design" with something that writes from PIO to the Memory. I used the QSYS Example (file: "A2gx125_qsys_pcie_gen1x4.zip" from Altera) to test the board, but I don't know how to continue. Please have mercy, normally I'm more into Hardware. I can do a little C and C++ but VHDL and FPGA's simply aren't my thing. It took me nearly a Month to get the Board to work somehow and run the "altpcie_demo" :oops:. Is there anyone out there who can help me a bit? This is how the QSYS-Project looks at the moment. I've only added the things beyond the blue line. Above the blue Line is the original QSYS-Project which transferd data from Memory to PCIe and otherwise:
Here is the very basic idea.Since you are using Qsys, you just need to connect PIO component(s) to the bar0. (you don't have to worry much about clock crossing, Qsys will take care) For the s/w side, you need to access this bar0 to read/write the 32bit PIO data.
If you want to read data from the PIO and write it directly to a memory location on the host side then yes reading from the BAR will do this.If you want to buffer the PIO data locally in memory on the FPGA then read it over PCIe then you would have to DMA the data from the PIO into the local memory first, then read the data from the memory either by reading directly from the BAR or kicking off a memory --> PCIe transfer using the DMA. By any chance are you trying to sample data from the PIO? If so I wouldn't recommend this approach since the sampling interval will not be constant. You would be better off using a FIFO with one side MM/ST that you can read data out of with the other side clocked at the sampling frequency and connected to the I/O.
--- Quote Start --- By any chance are you trying to sample data from the PIO? If so I wouldn't recommend this approach since the sampling interval will not be constant. You would be better off using a FIFO with one side MM/ST that you can read data out of with the other side clocked at the sampling frequency and connected to the I/O. --- Quote End --- Well this is exactly what I want. I want to read a 32Bit bus with 50MHz on the HSMC Breakout board into the Memory (or better a FiFo-Buffer) on the Board to transfer the datas later via PCIe to my software. For this I need a Buffer of approximately 32MiB to store datas of 500ms. The only Problem: I have no doubt how to create it on a FPGA! But I have the order to do this and so I must ask you how I can achive this. Sorry. So I have to take one of the FiFo-Modules and place it between the PIO and PCIe. But I must convert from MM to ST and back because the PIO and the PCIe are MM and the FiFos are ST, right? Errr, HOW? This is the Main Idea:
I would eliminate the PIO since it doesn't add anything and just makes the design more complicated. In Qsys just add a FIFO with the write port exported to the top. Wire up your 32-bit data to the writedata signal of the FIFO, drive the enable bit high when you want to sample. For the read port of the FIFO just hook it up to the DMA. You could also make your own FIFO component so that you can enable the sampling using a CSR access (FIFO are one of the easiest components you can create for Qsys so don't let component creation scare you)The reason why you don't want to sample directly from a PIO is because you can't ensure the time between samples will be constant (you don't know when the master will issue the reads). Working with a constant interval between samples is way less complicated than variable interval data (especially when you don't know what the interval time is). By sampling directly into a FIFO you just have to ensure the DMA can keep up with the sampling rate so that the FIFO doesn't overflow, the interval between samples is handled automatically by the write enable of the FIFO itself. So for what you are trying to do this would be a better data path: I/O --> FIFO --> mSGDMA --> SDRAM (connected to FPGA) --> mSGDMA --> PCIe --> Host memory To do this you just need to maintain a pair of descriptors, one for the first transfer into the FPGA local memory and the other to transfer the 32MiB of data to the host. The software with the design already does the latter so you would just need to add the part that does the local buffering (read from FIFO write to SDRAM). How you write that in the host application I have no idea since I'm not familiar with the application or Jungo drivers.
--- Quote Start --- I/O --> FIFO --> mSGDMA --> SDRAM (connected to FPGA) --> mSGDMA --> PCIe --> Host memory --- Quote End --- I think the Datas have not to be stored in SDRAM. Since the FiFo can store more than 8000 data packages. So I think this will do the trick: I/O --> FIFO --> mSGDMA --> PCIe --> Host memory I just have to pick up the Datas very fast. And with the FiFo directly attached ti PCIe (via mSGDMA) I have only one adress where the Data is stored and don't need to build another Storage-Structure in the SDRAM. (Correct me if I'm talking absolutely bullsh**.) And I don't have to move the data internally to SDRAM. The only usable FiFo with MM is the On-Chip FiFo which I have now connected as shown beyond. The In-Clock will be later exported and connected to the external clock source of my testdevice. I think with enable bit you mean the "avalonmm_write_slave_write" bit. Can I connect it (externally) to clk_in to automatically trigger writing with 50MHz? Now there is another problem I don't understand: how do I connect the exported Ports to the HSMC-connectors. Normally I would use my soldering iron but I think my boss will kill me if I start soldering on the board :D. OK in Pin Planner, but how does it come that there is no Node or something for FiFo to assign a pin to? What must I do to see the FiFo-Ports in Pin Planner? PS: Don't I need a bridge or something to translate the generic bus into a avalon interface?
I'm running mad with this!OK, I created a bdf-File where I connected the PIO Inputs to a Pin PIOIn[31..0]. Then I created a node in Pin-Planner with the same Name and in the "Set Up Top-Level-Design File" I declared them as Input. Then I typed in the Pins on each Port of the PIO (PIOIn to PIOIn). Back in the bdf-File there was a Box which shows me the Pins and beyond them the Signal I want to use (3.3-V LVTTL). But the Assignment-Editor shows the PIOIns always as unknown. Must I create a Top-Level-Design File? I have tried this but it always destroys the Design because there seem to be some pins that are assigned to several Inputs/Outputs. Is there anybody out there who can give me a dumba*s-Manual. I already tried to use the Help and read in the Altera Manual but all it says to me is: "The Pin Planner is a thing to plan your pins." Please HELP!!
The next Problems:1. I can't restore the Factory settings. The Nios 2 command shell tells me that the Image I want to write on the board is too big for the device. So I can't use the restore.sh script. I have installed the "ArriaIIGX Development Kit 11.0". And try to run the factory recovery because the LCD only shows black rectangles. 2. The Board Test System doesn't run either. It always tells me: "No USB Blaster detected." But I can load the *.sof Files via USB Blaster to the board and the Quartus II Programmer doesn't send such errors. Does anybody know a solution for this?
Finally I made it!!!! (Somehow)I now have a design to write a generic 32-Bit Bus with clock, write-enable and reset to a FiFo and read the FiFo from my computer via PCIe. Thank You BadOmen for the advice.
--- Quote Start --- Finally I made it!!!! (Somehow) I now have a design to write a generic 32-Bit Bus with clock, write-enable and reset to a FiFo and read the FiFo from my computer via PCIe. Thank You BadOmen for the advice. --- Quote End --- Hi Steffen,I have the same work to do and meet too many problems:((i , a green hand for PCIE) : when i open the demo"a2gx125_qsys_pcie_gen1x4"and add the fifo component like yours,i don't know what should i do next . Could you give me some guides?:oops:
I'm so sorry. I didn't watch this forum for half a year.I'm a student and had some other studies to do in the summer semester. Do you still have the problem?