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PLL Reconfiguration using mif for strarix 10

minjoolee
Employee
411 Views

 

Hi ) 

 

I want to generate PLL with mif setting for 5 clock speed. 

for example, input clock is 100MHz,  I want to generate PLL which have 2 output clks.

but it should be reconfigurable with mif files.

Output clock used 30,40,50,60,60 Mhz 

 

 

minjoolee_0-1646040673872.png

 

2) 

 

minjoolee_1-1646040798406.png

 

minjoolee_2-1646040822774.png

 

with 2 options, 1 mif file is generated for 30 Mhz and 40 Mhz.

 

minjoolee_3-1646040881576.png

 

 

minjoolee_4-1646040909702.png

 

with this , MIF can be updated. 

 

This is OK , but for the RTL simulation how to change from 20 Mhz to 60Mhz ?

 

minjoolee_5-1646041028806.png

 

 

if 60Mhz option start 48 = 30 (hax) 

 

minjoolee_6-1646041080345.png

 

 

I put  address = 0 ( mig option is [9:8] = 0 ) 

        and mgmt_writedata = 30(hex )  

                mgmt_write 

 

than waitrequest is 0 --> 1   and again 1-->0 

 

 but output clock is what I wanted.

 

Can u tell me   how to do reconfiguration PLL speed using mif ?

 

 

 

 

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6 Replies
Farabi
Employee
398 Views

Hello, 

 

For PLL reconfiguration using mif , you may want to refer to AN454. I attached here for your usage. Figure 7 on page 12 of AN454 might have explanation on how you can put the mifs into each RAMs and call the mifs when you want to perform PLL reconfig. 

 

I also attached Stratix IV design example, it might be old ref design, but it will give you an idea on how to do the PLL reconfig from multiple mifs.

 

regards,

Farabi 

Farabi
Employee
398 Views

files attached.

minjoolee
Employee
374 Views

 HI, I following guideline. 

 

 I attached what I show pdf. 

 

 and waveform , which shows PLL clock is changed but what I wanted value.

 

So I believe that I have a problem to set mif file or use it.

 

 

minjoolee_0-1646216168008.png

 

 

 

Farabi
Employee
298 Views

Hi Min Joo, 

 

Based on our conversation on phone, we do believed that this is simulation model issue for VCS. I am checking on modelsim if this can be done correctly. While checking this, I will file bug report to model owner so they can fix this. 

 

regards,

Farabi

Farabi
Employee
158 Views

Hello, 

 

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

 

regards,
Farabi

minjoolee
Employee
149 Views

HI ,

 

Generation is DONE, Synthesis is DONE,

 

but I can't PLL output speed with verdi simulator. 

 

that is why I try to find out how to generate .

 

still can't do that

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