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Altera_Forum
Honored Contributor I
1,208 Views

PLL on Altera DE3 Development Board doenst work

Hello everyone, 

 

im using the developement board altera DE3 (Stratix III , EP3SL150f1152C2N) for my master thesis. Im trying to use a PLL to get a higher clock. Therefor im using the internal 50 MHz clock as an input. Im using Quartus II 11.0 SP 1 for programming. I used QSYS --> PLL --> Avalon ALTPLL to generate the required PLL files. I want to use the higher clock rate to toggle an LED as a test. I used this code for this. 

 

 

library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; Entity Test8 is PORT( CLK : in std_logic; LEDG : out std_logic:='1'; DB0 : out std_logic; DB1 : out std_logic ); end Entity Test8; architecture Behavioral of Test8 is Component PLL is PORT( clk : in std_logic; locked : out std_logic; c0 : out std_logic ); End Component; SIGNAL CLK_100 : std_logic; Begin PLL_inst : PLL PORT MAP(CLK, OPEN, CLK_100 ); DB0 <= CLK; DB1 <= CLK_100; process(CLK_100) Variable cnt : integer :=0; begin if (CLK_100'event and CLK_100='1') then cnt:=cnt+1; if (cnt=100000000) then LEDG <= '1'; elsif (cnt=200000000) then LEDG <= '0'; cnt:=0; end if; end if; end process; End Behavioral;  

 

and  

 

-- PLL.vhd library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity PLL is Port( clk : in std_logic :='0'; locked : out std_logic :='0'; c0 : out std_logic ); end entity PLL; architecture rtl of PLL is component PLL_altpll_0 is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset read : in std_logic := 'X'; -- read write : in std_logic := 'X'; -- write address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address readdata : out std_logic_vector(31 downto 0); -- readdata writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata c0 : out std_logic; -- clk areset : in std_logic := 'X'; -- export locked : out std_logic; -- export phasedone : out std_logic -- export ); end component PLL_altpll_0; begin altpll_0 : component PLL_altpll_0 port map ( clk => open, -- inclk_interface.clk reset => open, -- inclk_interface_reset.reset read => open, -- pll_slave.read write => open, -- .write address => open, -- .address readdata => open, -- .readdata writedata => open, -- .writedata c0 => open, -- c0.clk areset => open, -- areset_conduit.export locked => open, -- locked_conduit.export phasedone => open -- phasedone_conduit.export ); end architecture rtl; -- of PLL  

I can compile the project, the output DB0 gets the internal 50 MHz clock (checked with oscilloscope) but there is no signal on DB1 which means the PLL generates no signal at all. The LED keeps lit. 

 

Thanks in advance!
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5 Replies
Altera_Forum
Honored Contributor I
56 Views

It appears the physical PLL signal are not properly connected inside your PLL component (ie. clk => open). 

I don't understand why you used Qsys to generate the PLL component which is supposed to be controlled like an Avalon MM slave: from the code you posted it seems your design doesn't rely on an Avalon infrastructure.
Altera_Forum
Honored Contributor I
56 Views

I redid my project with the MegaWizard IP Manager. Just like before the project compiles without any error, but i dont get a higher clock out of the PLL. 

I used this code: 

 

library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; Entity Test9 is PORT( CLK : in std_logic; LEDG : out std_logic_vector (0 TO 7); DB1 : out std_logic_vector (0 TO 8) ); end Entity Test9; architecture Behavioral of Test9 is Component PLL is PORT( inclk0 : in std_logic; c0 : out std_logic; locked : out std_logic ); End Component; SIGNAL CLK_100 : std_logic; Begin PLL_inst : PLL PORT MAP(CLK, OPEN, CLK_100 ); DB1(0) <= CLK; DB1(1) <= CLK_100; process(CLK_100) Variable cnt : integer :=0; begin if (CLK_100'event and CLK_100='1') then cnt:=cnt+1; if (cnt=100000000) then LEDG <= "11111111"; elsif (cnt=200000000) then LEDG <= "00000000"; cnt:=0; end if; end if; end process; End Behavioral;  

 

and 

 

LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY PLL IS PORT ( inclk0 : IN STD_LOGIC := '0'; c0 : OUT STD_LOGIC ; locked : OUT STD_LOGIC ); END PLL; ARCHITECTURE SYN OF pll IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (9 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC ; SIGNAL sub_wire2 : STD_LOGIC ; SIGNAL sub_wire3 : STD_LOGIC ; SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); COMPONENT altpll GENERIC ( bandwidth_type : STRING; clk0_divide_by : NATURAL; clk0_duty_cycle : NATURAL; clk0_multiply_by : NATURAL; clk0_phase_shift : STRING; compensate_clock : STRING; inclk0_input_frequency : NATURAL; intended_device_family : STRING; lpm_hint : STRING; lpm_type : STRING; operation_mode : STRING; pll_type : STRING; port_activeclock : STRING; port_areset : STRING; port_clkbad0 : STRING; port_clkbad1 : STRING; port_clkloss : STRING; port_clkswitch : STRING; port_configupdate : STRING; port_fbin : STRING; port_fbout : STRING; port_inclk0 : STRING; port_inclk1 : STRING; port_locked : STRING; port_pfdena : STRING; port_phasecounterselect : STRING; port_phasedone : STRING; port_phasestep : STRING; port_phaseupdown : STRING; port_pllena : STRING; port_scanaclr : STRING; port_scanclk : STRING; port_scanclkena : STRING; port_scandata : STRING; port_scandataout : STRING; port_scandone : STRING; port_scanread : STRING; port_scanwrite : STRING; port_clk0 : STRING; port_clk1 : STRING; port_clk2 : STRING; port_clk3 : STRING; port_clk4 : STRING; port_clk5 : STRING; port_clk6 : STRING; port_clk7 : STRING; port_clk8 : STRING; port_clk9 : STRING; port_clkena0 : STRING; port_clkena1 : STRING; port_clkena2 : STRING; port_clkena3 : STRING; port_clkena4 : STRING; port_clkena5 : STRING; self_reset_on_loss_lock : STRING; using_fbmimicbidir_port : STRING; width_clock : NATURAL ); PORT ( clk : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); locked : OUT STD_LOGIC ); END COMPONENT; BEGIN sub_wire5_bv(0 DOWNTO 0) <= "0"; sub_wire5 <= To_stdlogicvector(sub_wire5_bv); sub_wire1 <= sub_wire0(0); c0 <= sub_wire1; locked <= sub_wire2; sub_wire3 <= inclk0; sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; altpll_component : altpll GENERIC MAP ( bandwidth_type => "AUTO", clk0_divide_by => 1, clk0_duty_cycle => 50, clk0_multiply_by => 2, clk0_phase_shift => "0", compensate_clock => "CLK0", inclk0_input_frequency => 20000, intended_device_family => "Stratix III", lpm_hint => "CBX_MODULE_PREFIX=PLL", lpm_type => "altpll", operation_mode => "NORMAL", pll_type => "AUTO", port_activeclock => "PORT_UNUSED", port_areset => "PORT_UNUSED", port_clkbad0 => "PORT_UNUSED", port_clkbad1 => "PORT_UNUSED", port_clkloss => "PORT_UNUSED", port_clkswitch => "PORT_UNUSED", port_configupdate => "PORT_UNUSED", port_fbin => "PORT_UNUSED", port_fbout => "PORT_UNUSED", port_inclk0 => "PORT_USED", port_inclk1 => "PORT_UNUSED", port_locked => "PORT_USED", port_pfdena => "PORT_UNUSED", port_phasecounterselect => "PORT_UNUSED", port_phasedone => "PORT_UNUSED", port_phasestep => "PORT_UNUSED", port_phaseupdown => "PORT_UNUSED", port_pllena => "PORT_UNUSED", port_scanaclr => "PORT_UNUSED", port_scanclk => "PORT_UNUSED", port_scanclkena => "PORT_UNUSED", port_scandata => "PORT_UNUSED", port_scandataout => "PORT_UNUSED", port_scandone => "PORT_UNUSED", port_scanread => "PORT_UNUSED", port_scanwrite => "PORT_UNUSED", port_clk0 => "PORT_USED", port_clk1 => "PORT_UNUSED", port_clk2 => "PORT_UNUSED", port_clk3 => "PORT_UNUSED", port_clk4 => "PORT_UNUSED", port_clk5 => "PORT_UNUSED", port_clk6 => "PORT_UNUSED", port_clk7 => "PORT_UNUSED", port_clk8 => "PORT_UNUSED", port_clk9 => "PORT_UNUSED", port_clkena0 => "PORT_UNUSED", port_clkena1 => "PORT_UNUSED", port_clkena2 => "PORT_UNUSED", port_clkena3 => "PORT_UNUSED", port_clkena4 => "PORT_UNUSED", port_clkena5 => "PORT_UNUSED", self_reset_on_loss_lock => "OFF", using_fbmimicbidir_port => "OFF", width_clock => 10 ) PORT MAP ( inclk => sub_wire4, clk => sub_wire0, locked => sub_wire2 ); END SYN;  

I get some Warnings like "No clocks defined in the Design", could this be the problem? 

 

Thanks in advance
Altera_Forum
Honored Contributor I
56 Views

When you instantiate the PLL don't use: 

PLL_inst : PLL PORT MAP(CLK, OPEN, CLK_100 ); 

 

but rather use the explicit port assignments: 

PLL_inst : PLL PORT MAP(inclk0>=CLK, c0>=CLK_100 );
Altera_Forum
Honored Contributor I
56 Views

Thank you very much! 

It works now!
Altera_Forum
Honored Contributor I
56 Views

That's because if you use the implicit port assignment, the external signals are connected to the component ports depending on the listing order. 

Then, according to the definition: 

Component PLL is PORT( inclk0 : in std_logic; c0 : out std_logic; locked : out std_logic ); End Component;  

when you instantiated PLL_inst : PLL PORT MAP(CLK, OPEN, CLK_100 ); 

you actually connected c0 to OPEN and locked to CLK_100 

 

Using the explicit assignment is the common practice and it is strongly recommended, since it avoids any confusion, especially when you need to modify the component definition.
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