PLL wrapped into QSYS platform designer

[Majo]

Hi,

I have Cyclone5 device and my design is based on QSYS structure. I have created my own QSYS module and this module has an PLL IP core inside.

In sdc file I have set "derive_pll_clocks -create_base_clocks" option but Quartus doesn't define that internal PLL IP and there is an error Warning (332086): Ignoring clock spec. Clock assignment is being ignored.

If I setup this PLL IP as an independent QSYS module there is no problem with defining it by Quartus.

Why Quartus cannot define this PLL IP when it is inside manual QSYS module?

Thanks for answer.

[sstrell]

Platform Designer does create SDC constraints automatically for some IP in systems, so that may be what's happening here.  Also, you don't mention what device you are targeting.  I think derive_pll_clocks is not required with the newest devices like Agilex 7.

Either way, you're seeing just a warning, so it can be ignored, unless your timing analysis is not correct.

[ShengN_Intel]

Hi,

Do you mean that you have created your own new component IP QSYS module in Platform Designer and that custom IP has an PLL IP core inside?

When creating new component IP, will need to add the Synthesis Files for analyzed right? Usually PLL IP core will have a .qip file to include all the file sets but this .qip file can't be analyzed by component editor. Probably this cause the problem. Why not you just setup the PLL IP as an independent QSYS module and then make necessary connection to your own created QSYS module IP in Platform Designer.

Thanks,

Best Regards,

Sheng

[Majo]

Hi,

Yes, you are right. It exactly I have done and wanted to be sure that is not good way to use PLL inside qsys component.

Thanks for your answer.