- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi, I met an Error when programming the Stratix 10 SX FPGA.
it shows the same as @Ppavan mentioned:
I am using Quartus Prime Pro 19.1
I am using Stratix 10 SX Dev Kit with Device: 1SX280HN2F43E2VG
Thanks for all help!!!
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
OHHH I solved this problem.
I checked the update package of the d5005 chip and searched for qsf file in openCL hardware manager, and changed power management setting in my project. The core error is a wrong address number of the slave device protected by the openCL interface.
Thanks very much!
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
Have you tried to use the sof file from dev kit installation package "https://www.intel.com/content/dam/altera-www/global/en_US/support/boards-kits/stratix10/soc/stratix10SX_1sx280uf50_soc_revB_htprd_v19.1_b240_v1.0.zip"?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Yes, I tried them as long as I met the error.
However, the setting in this design is not compatible with the FPGA I want to program onto, so it always fail.
Then I checked the qsf file in this package and reviewed the setting in my project according but it didn't work, too.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
OHHH I solved this problem.
I checked the update package of the d5005 chip and searched for qsf file in openCL hardware manager, and changed power management setting in my project. The core error is a wrong address number of the slave device protected by the openCL interface.
Thanks very much!
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
I am glad that to hear that the issue has been resolved.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I have the same issue with a Stratix 10 Dev Kit. I am so puzzled as to why intel Moderators do not capture the full and detailed solution like Xilinx Answer Records do. That way when others search for this problem and find this they could follow the detailed solution instead of being disappointed that Intel is just happy that Harriet5he found his solution, whatever it is. What about others who have the same issue? I have no idea what the solution is from this thread.
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page