Parallel Flash Loader on Stratix III & S3 DSP Dev Kit... Anyone have it working?

[Altera_Forum]

I have the S3 DSP Dev Board; tried to burn my own code into the on-board flash. 

 First problem was that Altera compiled the PFL .sof and Factory Recover .pof for an Engineering Sample of the EP3SL150, but my board has a production version of the device (different JTAG ID).  Altera sent me new plf.sof and recover.pof.  Using embedded USB Blaster, I followed the Dev Kit User Guide instructions.  PFL appears to load correctly. Then a new copy of recover.pof also appears to load correctly. Status messages and progress reports (Erasing FLASH address ... and Programming FLASH address ...) all look good.  When done, it says operation completed successfully. Upon reboot (factory config button or power cycle), nothing happens. No usable program loads; it just seems to be stuck in the conf/loading state forever.  Same problem with my own code as with their factory recover file.  Has anyone experienced or solved this?  ----  Also, the instructions are not specific about setting Rotary Switch SW3 during programming.  I had it in position 0 for all the trials above. If you want to put a different program in the flash at Page 1, do you change offsets when you convert .sof to .pof? Or do you just use the defaults (as if page 0) but change the rotary switch to the position of the page you want to program?  Thanks in advance.  jmj

[Altera_Forum]

Just an update: 

 It appears the new PFL .sof file Altera gave me was corrupted in transit or otherwise an incorrect file for this board.  The S3 DSP boards were apparently developed with Engineering Sample versions of the EP3SL150, and compiled with 7.2.sp1  The S3 non-DSP kits have files targeting production versions of the EP3SL150 and files were compiled with 7.2.sp3  I grabbed the PFL.sof file (as well as factory_recover.pof) from a non-DSP kit and used that to restore my DSP board. That much seems to work.  As a backup in case of emergency, the PFL is used as an example in the examples directory, so project files exist if you need to rebuild it yourself.  --------  As for the other issues, I'm still looking for clear answers on creating and programming .pof files into other pages of the flash (to power up with the rotary switch in other positions).  I successfully put the factory default program back into page 0. I can also put my own programs in page 0. When I put my own program into page 1, that worked, but it corrupted the factory default file in page 0.  Still looking for clarifications...  As a final goal, I want to be able to put different programs in each of the pages, and be able to change each page individually (without corrupting the others) AND ALSO be able to write one file with all 8 programs in one shot.  Ideally, half the programs would be encrypted, and half would not...

[Altera_Forum]

I have the same issue. 

 I have seen in the .map file generated when converting a .sof into a .pof file that pages don't correspond to fix addresses in the flash. by default, the design is loaded at address 0x0 whatever is the page number. This would explain that loading a new design overwrites the current ones even if the page number specified is different.  My guess is that you should define by your own the memory mapping of pages. As a design seems to be 0x5A_FAFF long, you could place it in a 0x60_0000 long page for example. Then, page mapping would be: - page 0: 0x0 - page 1: 0x60_0000 - page 2: 0xC0_0000 and so on  When you convert .sof into .pof, specify explicitly the address range occupied by your design by selecting "Block" address mode in the SOF data property window. Altera documents are very clear on that point.  I can not reload the factory design delivered with my development kit. It seems that it is not compiled for the appropriate version of EP3SL150. I'll ask Altera to send me a correct version. Furthermore, the .pof file of the factory design erases the whole flash content, thus all the other designs.  Maybe the best solution would be to have the source of the factory design so that we would be able to regenerate it with a correct configuration as like as for the PFL design.