Hi everyone!
I don't know am I asking question at right place, I need help with optimizing my FPGA project in terms of freqs. I am trying to generate chaotic signal on FPGA board, chaotic oscillator described as IIR filter with nonlinear module (fig. 1), to realize that I used parallel add module from basic functions catalog. I found information about parallel add module only for Stratix devices (fig.2) On my Cyclone® V SE 5CSEMA4U23C6N device I get about 150 MHz FMax (fig. 3) and without non linear module about 200 MHz, am I doing something wrong or Cyclone V is slower than old Stratix devices? Can you give me advice how can I get higher FMax for this project?
And sorry for my poor English.
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Dear sstrell
On your advice, I began to study timing analysis and I had several questions.
1. Do I understand correctly that setting the minimum and maximum delay constraints is necessary only for asynchronous combinatorial logic? Whether it is necessary to set, apart from the clocks constraints, the delay constraints for the synchronous register-comb logic-register case (fig 1), like set_max_delay -from [get_registers {x_1_3*}] -to [get_registers x_2_1d*] X ns?
2. Also, while reading the literature (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-timing-analyzer.pdf, page 44), I learned that a large number of outputs from one register can also limit the maximum frequency of the circuit. But I did not find the Design metrics in the timing analyzer in Quartus Light to automatically fix this problem, do I need to purchase the pro version for this?
3. Another question concerns fast and slow models in Quartus. If the time constraints are met for the fast model, but not for the slow model (fig 2), what should I do to make the crystal work in the fast mode?
