i am totaly stuck in the an 456 ap note. I'am using the pci express 7.1 ip with dma application note. when i generate at first the project with connecting nothing at the output of the dma, i can send 100 packets of 262140 B at a data rate of 200 MB/s (working with one lane) from the root complex memory to the hardware. every thing is ok The problem is that when i connect a fifo as an end point and i connect the fifo almost full on the rx_ws to generate a wait state on the reception stream the dma transfer fails when wait state are generated. Does any body can help me ?