Phased Clock

[VYoung]

Are there any Intel SoC FPGAs that provide a clock manager with different phased clock outputs? e.g. One 100 MHz input with four 200 MHz phased outputs (0 degree, 90 degrees, 180 degrees, and 270 degrees).  If yes, what is the FPGA family (i.e., Agilex, Stratix, Arria, MAX, Cyclone)?  And what is the device part number within the family?

[mabdrahi]

Hi Vincent,

I will look and try to get back to you with useful info soon as possible

[mabdrahi]

Hi Vincent,

here is what I found for PLL document

1) https://www.intel.com/content/www/us/en/docs/programmable/683130/23-1/introduction.html

2) http://www.altera.com/literature/ug/ug_altpll.pdf

I will get back to you with conclusion soon.

[lixy]

Hi VYoung,

Many FPGA devices supporting phase-shifting clocks, such as Agilex 7, Stratix 10, Arria 10, Cyclone 10, MAX 10 and so on. The phase shift is basically implemented by PLL and most of Intel FPGAs contains PLL.

For example, you can find out in Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook Chapter 4.2. Intel® Arria® 10 PLLs to know how we can implement the phase shift in Arria 10 device.

"The VCO frequency of the PLL determines the precision of the phase shift. The minimum phase shift increment is 1/8 (for I/O PLL) or 1/4 (for fPLL) of the VCO period. For example, if an I/O PLL operates with a VCO frequency of 1000 MHz, phase shift steps of 125 ps are possible."

https://www.intel.com/content/www/us/en/docs/programmable/683461/current/plls.html

Not sure if this answers your question?

Thanks & Regards,

Xiaoyan