Pin connection for P-Tile Avalon-ST for PCIe on Stratix10 DX110 FPGA chip?

[CQIAN11]

To Whom It May Concern,

I tried with the P-Tile Avalon-ST for PCIe hard IP on Stratix10 DX110 FPGA chip. However, the example design did not get the correct pinout connection for the hard IP.

And I am clear that the Series IO pins should be connected with the GXPL10A_* pins. But I am still not clear about the nPERST[L, R] PIN number. I can not find any documentation about the pin table for Stratix 10 DX. Is there any pin connection guideline or example for the PCIe Hard IP on Stratix 10 DX?

Thanks!

[Rahul_S_Intel1]

Hi ,

I made an example design for your reference, this will be give you better understanding about nPREST

[CQIAN11]

Hi RahlS，

Thanks for your example design. However, the device you created is Stratix10 DX 280 and I need to create a project with Stratix10 DX 110 which has different pinout numbers. Do you have any input for Stratix DX 110 FPGA Chip pinout connections for P-Tile Hard IP?

Thanks.

Best regards,

Collin​

[Rahul_S_Intel1]

may I have full part no:

[CQIAN11]

Sure.

-family Stratix 10

-part 1SD110PJ2F43E2VG

Thanks.​

[Rahul_S_Intel1]

KIndly find the attached design