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Pin location(s) doesn't show in .bdf file.

Altera_Forum
Honored Contributor II
878 Views

I'm working with a Stratix-III development kit (DK-DEV-3SL150N). I based my application on the one provided by the kit. With some modifications (through research), it seems to be working fine (i.e. ethernet, leds, lcd, etc...) using niosII 'simple socket server' application, etc...  

 

I'd like to start to define a .bdf file as part of the project, with a specific logic design. I used the pin definitions that come with the kit and everything compiles without error. 

 

The problem I'm having is that the pin locations, such as hsmb_d[0], do *not * show up after compilation. My 'really simple' test uses the breakout board that comes with the kit and defines hsmb_d[3..0] as output pins, alternate a bit pattern (0x5) using gnd and vcc symbols, then check the output (with 2.5V IO standard) with a voltmeter. Unfortunately, the voltmeter does *not* reflect the design. All outputs are at 0V, so I'm not convinced that it's operating correctly. 

 

Does anyone have a solution to this problem, know where I can look or what I'm doing wrong? 

 

Please advise,thanks in advance,
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Altera_Forum
Honored Contributor II
129 Views

OK, I found a solution. I cannot take full credit for it, because another post in the forum 

(http://www.alteraforum.com/forum/showthread.php?t=25485) started the process. I don't think it's the best solution (mine), but it works. So, if anyone has a better solution, please advise. 

 

Here's what I did: 

 

1. Created main.bdf file and make it the top-level entity. 

2. Created symbol file from stratixIII_3sl150_ dev_niosII_standard.v. 

3. Added symbol to main.bdf. 

4. Added SOPC pins as determined by symbol, i.e. ddr2_deva*. 

5. Added hsmb_d[3..0] pins (as output for my testing). 

6. Built design, takes ~15-20 minutes. 

 

I created an instance of the 'simple_socket_server' in NIOS-II and for the most part worked just fine. Still a long way to go for my final application. 

 

For further modifications: 

1. Modify the CPU in SOPC builder 

2. Generate cpu 

3. Modify stratixIII_3sl150_dev_niosII_standard.v, if necessary, with new pin assignments. I used TextPad on Windows. 

4. Regenerate symbol file from stratixIII_3sl150_dev_niosII_standard.v. 

5. Update symbol for stratixIII_3sl150_dev_niosII_standard in schematic. 

6. Rebuild design, takes ~15-20 minutes. 

 

I know, seems like a pain, and it is, but it worked, for now until I can find something easier. I tried adding the symbol stratixIII_3sl150_ dev_niosII_standard_sopc, but ran into problems when building. 

 

Thanks, 

/david
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