Please provide recommendation on which IP/protocol to use for inter-FPGA connectivity while developing prototyping system based on multiple Stratix10 FPGAs - i.e. somthing functionally similar to Xilinx's chip2chip interface IP. Thanks.

[Deshi_Intel]

HI,

It really depends on your project application requirement.

Intel FPGA doesn't has unique IP core to FPGA to FPGA data transfer but you can consider using common industrial IP for the same purpose.

For instance :

1. For date rate > 1G - You can consider Ethernet IP
2. For data rate around 1G - LVDS IP
3. For data rate < 1G - Either PHYlite IP or GPIO IP

Thanks.

Regards,

dlim

[Mani]

Thanks for your response.

1) Are there are any reference designs or ANs for the 3 options you've suggested; If so, can you please provide the links ?

2) Can we use the Auroro interface IP for chip-to-chip interconnection for Stratix10 FPGAs ? Are there any ref. designs/ANs for that ?

Thanks & regards,

Mani

[Mani]

Hello, I noticed from Intel FPGA info. site literature that Serial Lite-III IP is supported in A10/S10 devices – which can be used for board-to-board interfacing. However, it is not mentioned in the 3 options you mentioned below; Can you please comment on that ? Thanks & regards, Mani

[Deshi_Intel]

Hi Mani,

I am simply explaining example to you and I quote Ethernet protocol as example.

Intel FPGA supports a huge variety of high speed protocol as shown in below link. It's really up to user preference on which protocol to pick that suit your design requirement.

• https://www.intel.com/content/www/us/en/programmable/solutions/technology/transceiver/protocols.html

I hope I clear your doubt now.

Thanks.

Regards,

dlim

[Mani]

Thanks. Regards, Mani

[Deshi_Intel]

You are welcome !

[Deshi_Intel]

HI Mani,

Pls see my respond below.

1) Are there are any reference designs or ANs for the 3 options you've suggested; If so, can you please provide the links ?

• There should be some reference design around. You can just google for it.

2) Can we use the Auroro interface IP for chip-to-chip interconnection for Stratix10 FPGAs ? Are there any ref. designs/ANs for that ?

• Auroro looks to me like a Xilinx IP. Why would Intel FPGA support Xilinx IP since they are competitor. :)
• So, short answer is no.

Thanks.

Regards,

dlim