FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
5924 Discussions

Please resume support for Altera case 00351373 Cyclone V SOC Eval board

NGord
New Contributor I
‎09-05-2018 08:04 AM
1,168 Views
 
0 Kudos

Link Copied

3 Replies
JohnT_Intel
Employee
‎09-07-2018 04:19 AM
366 Views

Hi,

 

Please follow the guide in https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd10312012_472.html to resolved the issue.

0 Kudos
Copy link
NGord
New Contributor I
‎09-07-2018 09:36 AM
366 Views
Hi That doesn’t work for me: This is what I have. [cid:image001.png@01D44694.C54F7510] [cid:image003.png@01D44696.67A4A870] [cid:image004.png@01D44696.67A4A870] I am launching Board Test System from 14.1 and still get [cid:image002.png@01D44696.AE8BE730] Regards Nigel
0 Kudos
Copy link
JohnT_Intel
Employee
‎10-08-2018 01:19 AM
366 Views

Hi,

May I know if you have multiple Quartus installed? Have you try the workaround using Nios II Command for 14.1 in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/support/kdb/downloads/rd01292013_416/setting_up_environment_variables_for_gui.pdf "Additional Option" chapter?

0 Kudos
Copy link
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.