Possible to set Cyclone IV GX differential I/O pin to 3.3 Volts?

[Altera_Forum]

I have a Cyclone 4 GX Development board, and I would like to set the Clock input on on Bank 5, Dedicated Clk input on pin T29 and T30 to differential I/O 3.3V. 

 Yes..... you are right in asking yourself!!  But .. But.. the Cyclone 4 GX Development kit only goes to 2.5 volts?? :eek:  Solution, I have modified the input power supply to the Cyclone 4 GX chip at 3.3 volts, for my custom board ADC interface, on Banks 5/6.  Now, My problem, is that the Data clock output from my ADC, is a differential signal, And I would like to interface it with my FPGA Cyclone 4 GX, at the 3.3 volts differentially.  Is there any easy way to do this? Other than, Use a different ADC chip! duh:rolleyes:. And or adding extra logic transceiver to the DCO pins.  Thanks. Mike K

[Altera_Forum]

1. There's no problem to drive inputs in a 2.5V bank with 3.3 V. 

2. I wonder which IO standard is involved with "3.3 volts differentially". I would expect a LVDS standard. It's voltage levels are independent of the driver supply voltage.

[Altera_Forum]

Well that's my issue..  

 I have tried with the LVDS Signal. When I select in the pin planner the LVDS Signal I get this error.  ---------------------------------------------  Error (169029): Pin DATA_BUS_CLK_O_FRM_ADC is incompatible with I/O bank 6. Pin uses I/O standard LVDS, which has a VCCIO requirement incompatible with that bank's VCCIO setting or its other pins that use VCCIO 3.3V.    Info (169073): Pin DATA_IN_FROM_ADC[0] in I/O bank 6 uses VCCIO 3.3V  Info (169073): Pin DATA_IN_FROM_ADC[1] in I/O bank 6 uses VCCIO 3.3V  Info (169073): Pin DATA_IN_FROM_ADC[2] in I/O bank 6 uses VCCIO 3.3V  Info (169073): Pin DATA_IN_FROM_ADC[3] in I/O bank 6 uses VCCIO 3.3V  Info (169073): Pin DATA_IN_FROM_ADC[4] in I/O bank 6 uses VCCIO 3.3V  Info (169073): Pin DATA_IN_FROM_ADC[5] in I/O bank 6 uses VCCIO 3.3V  Info (169073): Pin DATA_IN_FROM_ADC[6] in I/O bank 6 uses VCCIO 3.3V  Info (169073): Pin DATA_IN_FROM_ADC[7] in I/O bank 6 uses VCCIO 3.3V  Info (169073): Pin DATA_IN_FROM_ADC[8] in I/O bank 6 uses VCCIO 3.3V  Info (169073): Pin DATA_IN_FROM_ADC[9] in I/O bank 6 uses VCCIO 3.3V  Info (169073): Pin DATA_IN_FROM_ADC[10] in I/O bank 6 uses VCCIO 3.3V  Info (169073): Pin DATA_IN_FROM_ADC[11] in I/O bank 6 uses VCCIO 3.3V  Info (169073): Pin DATA_IN_FROM_ADC[12] in I/O bank 6 uses VCCIO 3.3V  Info (169073): Pin DATA_IN_FROM_ADC[13] in I/O bank 6 uses VCCIO 3.3V  Info (169073): Pin DATA_IN_FROM_ADC[14] in I/O bank 6 uses VCCIO 3.3V   My other pins are using 3.3 volts, for both input and outputs.... ----------------------------------------------   This goes back to my iniitial question, Is there a way to set pins T29/T30 on the cyclone 4 (Diffclk_3p) to accept a differential input? Even tho the VCCIO is set to 3.3V from that bank6?  Since I am new to the Cyclone 4 chip, I am not doing something simple. Or that I am forgetting something. I am looking at the I/O Buff mega-function, for some solutions. still researching this.  Can you set the pin input voltage different from the assigned VCCIO for that bank? In my mind and reading the docs? a big NO.  Again, I am lost. To me You should be able to set the voltage level to almost anything on an __Input__ pin. But in this case not Differentially. But You do run the risk of damaging your device if your signal level goes over the designated value. (which in my case is possible, hence 3.3 Volts.)  Thanks for you much valued input. Mike K

[Altera_Forum]

Hi FvH! 

 I solved my problem. The issue is that I used the DiffCLK Pins for the input of my Outputted Data Clock out of my ADC board.  What I should have used instead is a regular Diffio pin.  So after changing the pins to the regular diffio pins, U27,U28 for example and setting the I/O Standard to LVDS. it compiled fine.  Well time to get out the soldering iron! and hack my board. :cry:  Thanks. Mike K

[Altera_Forum]

Sorry I meant FvM... 

 Mike K