Power up and down sequencing for MAX 10 Devices

[ChetanKarkera]

Hello,

Could you please confirm whether power sequencing is required for Max10 FPGAs?

While most related documents indicate that it is acceptable not to use power sequencing, there is one design guideline document that suggests the use of power sequencing for improved reliability.

" Design power sequencing and voltage regulators for the best device reliability—
although power sequencing is not required for correct operation, consider the
power-up timing of each rail to prevent problems with long-term device reliability
if you are designing a multi-rail powered system." 

https://cdrdv2-public.intel.com/666778/m10_guidelines-683196-666778.pdf

[Fakhrul]

Hi ChetanKarkera,

There's no power up sequence requirement for MAX10. You may refer to the Intel® MAX® 10 FPGA Configuration User Guide statement for Table 23 on page 31 on page.

You can also refer Intel® MAX® 10 Power Management User Guide fro more detailed information regarding power management of MAX 10 device.

Regards,

Fakhrul

[Fakhrul]

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