FPGA, SoC, And CPLD Boards And Kits
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Power up the VCCR_GXB and VCCH_GXB rails of stratix 10 L-tile

SDe_J
New Contributor I
861 Views

I am trying to program a stratix 10 L-tile dev kit using Quartus 18.1.

 

I can compile the project, when when I try to program the board, It gets to 13%, then fails.

 

I found this page: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/component/2019/error---device-has-stopped-receiving-configuration-data-error-me.html

 

Which seems to be the issue I'm having, but I'm not sure how to actually apply the assignments from the workaround.

 

Thanks for the assistance.

 

 

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Rahul_S_Intel1
Employee
625 Views

As a first debugg step can you reduce the speed of the Jtag clock

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Shark121
Novice
564 Views

Hello,

 

I met the same problem with you, have you solved with it? Thank you!

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