Power up the VCCR_GXB and VCCH_GXB rails of stratix 10 L-tile

[SDe_J]

I am trying to program a stratix 10 L-tile dev kit using Quartus 18.1.

I can compile the project, when when I try to program the board, It gets to 13%, then fails.

I found this page: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/compon...

Which seems to be the issue I'm having, but I'm not sure how to actually apply the assignments from the workaround.

Thanks for the assistance.

[Rahul_S_Intel1]

As a first debugg step can you reduce the speed of the Jtag clock