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Problem Implementing clock in Cyclone II (Altera-DE2)

Altera_Forum
Honored Contributor II
2,021 Views

Hello, I want to generate a clock with 50% duty cycle, but the frequency must be 9999 Hz <= f < 10000 Hz. 

I tried implementing with counter division and multiplication, but can't seem to find the way. 

 

Is there any methods i didn't know to do that? Thanks before.
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8 Replies
Altera_Forum
Honored Contributor II
151 Views

you can watch this video to get an idea http://www.youtube.com/watch?v=t4fwna3-gi8

Altera_Forum
Honored Contributor II
151 Views

Does the Cyclone II support this?

Altera_Forum
Honored Contributor II
151 Views

Is this clock to be used external to the FPGA or just internally?

Altera_Forum
Honored Contributor II
151 Views

Thanks, alex96, but actually i've seen that video before and it didn't help because i couldn't see the "Altera PLL" GUI he's using, i guess it was meant for Cyclone V not II. Or did I miss anything? And yes i've got the idea but i have trouble here in implementing. 

 

Galfonz, from what i read it seems that there's no internal PLL cascading in Cyclone II, and it's for Cyclone III and above who has it in megafunction. But, i think there's must be a way to implement the "cascading" part (referring to the video from alex96), since both Cyclone III and II have 4 PLLs. 

 

And Tricky, i'm going to use the clock as PWM counter and porting it to GPIO for 9999 Hz PWM.
Altera_Forum
Honored Contributor II
151 Views

Hi, 

 

because it is Christmas. A simple clock divider you simply need to change the divider variable to the correct number. It depends from your ref clock and what clock you want. Alternatively, you can use a PLL using the megawizzard. 

 

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; ENTITY counter IS PORT( CLK : IN STD_LOGIC; CLR : IN STD_LOGIC; DIV_CLK : OUT STD_LOGIC ); END ENTITY counter; ARCHITECTURE logic OF counter IS BEGIN PROCESS(CLK, CLR) VARIABLE DIVIDER : UNSIGNED(23 DOWNTO 0) := (OTHERS => '0'); BEGIN IF CLR = '0' THEN DIVIDER := (OTHERS => '0'); ELSIF rising_edge(CLK) THEN DIVIDER := DIVIDER + 1; IF DIVIDER = "011111111101001000000000" THEN DIVIDER := (OTHERS => '0'); DIV_CLK <= '1'; ELSE DIV_CLK <= '0'; END IF; END IF; END PROCESS; END ARCHITECTURE logic;
Altera_Forum
Honored Contributor II
151 Views

If you insist for two PLL then you need to use external path in Cyclone II... 

you can use one prescaler to create input clock for PLL
Altera_Forum
Honored Contributor II
151 Views

Doing so might be problematic. Verify that the output Jitter and waveform quality are acceptable to whatever you are feeding it to.

Altera_Forum
Honored Contributor II
151 Views

Okay guys thanks for the explanations and code, in the end I'm using clock division (verilog) + PLL (megawizard, 1 PLL without cascading) for now, while I'm stuck combining the code I made with the megawizard haha. It's a pleasure if somebody give me an easy way to understand megawiz.

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