Problem getting started with DE0-Nano

[Altera_Forum]

Hi, 

I'm a complete noob with FPGAs. I wanted to learn how to use them and decided to just jump in, so I got the DE0-Nano and have programmed it with several tutorials. I've even gotten it to drive a 16x32 RGB LED matrix from AdaFruit (which is pretty cool). I've tinkered around by modifying other people's VHDL and have done a few very simple VHDL programs from scratch by hooking the key buttons to the LEDs (yeah, baby steps). Now it's time to graduate to something more complex. I've got the LED matrix app and an accelerometer demo that both work fine individually. I want to eventually drive the LED matrix with the accelerometers but for now I'll settle for just instantiating the 2 independent apps at the same time. But when I do this, it appears that the SPI interface to the accel chip doesn't work (the on-board LEDs don't change when I tilt the board). I'm struggling to understand how the 2 apps could interfere with each other but I'm a bit out of my depth here (understatement). Here's what I understand are the major components: 

• LED Matrix 
• JTAG interface to the host computer 
• SDRAM (frame buffer for the matrix) 
• GPIO (interface to the LED matrix) 
• Accelerometer Demo 
• SPI (apparently uses an altpll) 
• Accel sensor 
• On-board LEDs 

 By trial and error, I found that if I don't instantiate the JTAG interface, the accel demo works. But the JTAG is the only way I can load the frame buffer for the matrix. I'm at a loss! Can anyone help clue me in on how the JTAG and SPI could conflict? When I instantiate everything, I get no compiler errors but I do see this warning which I can't decypher:  Warning (332060): Node: ledctrl:U_LEDCTRL|clk_div:U_CLKDIV|clk_out was determined to be a clock but was found without an associated clock assignment. Warning (332060): Node: clk_in was determined to be a clock but was found without an associated clock assignment. Warning (332056): PLL cross checking found inconsistent PLL clock settings:  Warning (332056): Node: U_SPIPLL|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000  Warning (332056): Node: U_SPIPLL|altpll_component|auto_generated|pll1|clk[1] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.  Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)  Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)  Any help would be greatly appreciated! Let me know if I need to post more info.

[Altera_Forum]

The cyclone IV has multiple PLLs but I have a vague suspicion that both of your codes are trying to configure the same PLL.

[Altera_Forum]

--- Quote Start ---  The cyclone IV has multiple PLLs but I have a vague suspicion that both of your codes are trying to configure the same PLL.  --- Quote End ---    That sounds like a good lead. How would I even specify which PLL to use? As you can imagine, the JTAG interface and SPI PLL components were not written by me but I'm getting up to speed reading the Verilog and VHDL. Thanks.