Hi,
I am trying to interface the Texas Instruments ADC eval board to Arria 10 SoC using FMC+ to FMC interface. The interface uses JESD204B IP to receive the sampled data from ADC to the Transceiver PHY. I am using altera 10 design example from ti (
http://www.ti.com/lit/zip/slac748) to test the interfacing (); I follow the steps mentioned in the user guide (attached) to compile the design example, program the eval board, and analyze the data received using Signal Tap Logic Analyzer. I am providing a 250MHz sinusoidal signal at Channel A at the ADC. I am expected to see some data, but I see nothing. The only change I have made is assigning the device name to 10AS066NF340E2SG from 10AX115S2F45I1SGE2 and the corresponding pins in pin planner, which compiled with no error. I am wondering if you could help me in figuring out the problem. I find that the
dev_sync_n signal is low; but I am not sure why. PFA.
Thanks
