Problem in interacing TI ADC eval module (ADC12DJ3200EVM) with Arria 10 SoC.

[Altera_Forum]

Hi,  

 I am trying to interface the Texas Instruments (TI) ADC eval board to Arria 10 SoC using FMC+ to FMC interface. The interface uses JESD204B IP to send the data sampled at the ADC to the Transceiver PHY. I am using the arria 10 design example provided by ti (http://www.ti.com/lit/zip/slac748) to test the interfacing. TI also provides the user guide (attached) to follow the steps for programming the ADC eval board using GUI provided, compiling the design example, and observing the output using Signal Tap Logic Analyzer in Quartus Prime. I have made no changes except reassigning the Arria 10 device name from 10AX115S2F45I1SGE2 to 10AS066N3F40E2SG, and changing the corresponding; it compiled smoothly. I am feeding in 250MHz sinusoidal signal at the Channel A of the ADC. I am expecting to see some output at the Signal Tap logic analyzer, but I see nothing. I double-checked that everything is correct, but I still don't see any output. I find ( in the signal_tap_output) that the dev_sync_n output is LOW (and it is supposed to be HIGH), thus the synchronization is not happening, which might be the reason behind no sampling at the ADC. Could you help me in figuring out the problem in ADC interfacing?  Thanks  Attachments:  user guide for testing the ADC interfacing in JMODE0 and JMODE2 expected_signal_tap_output signal_tap_output test_setup