Problem in using PLL

[Altera_Forum]

Hi,I am using this chip Cdcs502 from Ti.I am running a 27Mhz crystal and connecting Capacitor load of 35pF ,with FS=0,the output is a clock pulse with 0.8 low and 2.1 high,i think this is fine.But the problem is when i do FS=1,the frequency gets 108Mhz but the amplitude becomes very low , the peak to peak amplitube is 800mV having a DC offset of 1.6 V...Kindly help me with this..] 

 I need this 108Mhz signal to clock my EPM7064S.   Kindly help!!

[Altera_Forum]

Sounds simply like a measurement artefact, either due to a slow oscilloscope or inappropiate probing.

[Altera_Forum]

well i have checked the oscilloscope and probing method...i dnt think anything wrong with these

[Altera_Forum]

According to the datasheet, CDCS502 has 32 ohm driver impedance. It should be able to drive regular capacitive loads. However I don't have the chip and check it's behaviour. 

   --- Quote Start ---  with FS=0,the output is a clock pulse with 0.8 low and 2.1 high,i think this is fine.  --- Quote End ---   This is far from keeping LVCMOS level specification. Sounds like you connected a heavy resistive load to output, you should operate it basically unloaded.

[Altera_Forum]

I am operating it no load at all except i see the out on oscilliscope....so still cant figure out the problem