Problem: interfacing DDR2 with Terasic DE-4 CALIBRATION FAILURE

[Altera_Forum]

Hi everyone! 

I've spent at least 6 week trying to interface a DDR2 1GB SO-DIMM RAM (200 Pin, 800 Mbps, CAS latency 6) with my (university) board Terasic DE-4. Above this board is mounted a Stratix IV EP4SGX230KF40C3 (speed-grade 3), and we have two socket for the memory RAM on the Terasic DE-4 board.  To interface my memory I used Quartus Prime 13.0 sp1, so with Megawizard Plug-In Manager I used the Controller Uniphy 13.0 (400 MHz for memory and 100 MHz for PLL reference clock). Anyway, I wrote a verilog code and I simulated it, it looked fine, and it worked as I wanted. When I tried to compile and run my code on the Board it didn't work because of a calibration failure.  I'm sure that my code works on the board, the simulation tells me that the controller works fine, but when I see what happen with the Signal Tap Analyzer I see that the local_cal_fail signal is asserted... and I don't know why. I've obviously made a pin planning, using the tcl script that comes from the Controller Uniphy wizard, and I've manually set all pin that the FPGA use to communicate with the DDR2 (DQ, CK, DQS, DM etc...). Moreover, I set the pin for oct_rup and oct_rdn, i.e. on chip termination, at 50 Ohm parallel termination in assignment editor and I assigned two pin on the FPGA with a proper voltage standard.  With the tool: External Memory Debug Toolkit I can read that the calibration failed during the first stage: Read Guaranteed failure.   So... Is there anyone who can tell me any guideline to verify that my work chain is good? Anyone that can give me any hint? Would be my problem due to a Board Skew not considered in the Altera Standard settings?   Thanks to everybody will give me an answer,  King Regards!  Gennaro  PS: I'm an Italian student, this is my first thread, and this is my first experience in a complex project with an FPGA, sorry if my english isn't good enough! I hope I gave enough information about the issue. Don't hesitate to ask more information to solve the issue.

[Altera_Forum]

Hi Gennaro, actually, we have never implemented simulation as you tried, thus not so clear about this part temporarily, here my partner advised another attached example, but an actual one for your reference, it can be executed instead. Anyway, hope it's of a little help. May I know your university is? I'm more than pleased to assist in further, free to drop me a line if you think necessary or more convenient, any queries, thanks!  

 BR Nikita_Terasic, for European region