Problem running MAX 10 - Single-Port Triple Speed Ethernet and On-Board PHY Chip Design Example

[hon1]

Hi, I tried to run the example (MAX 10 - Single-Port Triple Speed Ethernet and On-Board PHY Chip Design Example (intel.com)) on Quartus 18.0. When I generate HDL using Platform designer, I gotten the following error messages. 

Error: qsys_top.aso_splitter_0: Component aso_splitter 1.0 not found or could not be instantiated
Error: qsys_top.error_adapter2_0: Component error_adapter2 1.0 not found or could not be instantiated
Error: qsys_top.eth_gen_0: Component eth_gen 1.0 not found or could not be instantiated
Error: qsys_top.eth_mon_0: Component eth_mon 1.0 not found or could not be instantiated
Error: qsys_top.st_mux_2_to_1_0: Component st_mux_2_to_1 1.0 not found or could not be instantiated

Can anyone point me to the fix for this error messages?

[ZiYing_Intel]

Hi hlseck,

Just wan to confirm that your are using the example design only or got do some modification into the example design?

Best regards,

Zi Ying

[hon1]

Hi ZiYing,

I am using as the example design as downloaded with no modification. 

Best regards,

hlseck

[ZiYing_Intel]

Hi hlsleck,

I try run the example design that you mentioned by using 18.0 std. The design was compiled successfully and there is no error message from my side.

Can you share your .qar file? So that I can try debug the issue from my side.

Best regards,

Zi Ying

[hon1]

Hi ZiYing,

I have downloaded the files directly from the link (https://www.intel.com/content/www/us/en/design-example/714819/max-10-single-port-triple-speed-ethernet-and-on-board-phy-chip-design-example.html). I can compile the project on Quartus 18 standard edition.

It is when I use Platform Designer to open qsts_top.qsys, I got the error messages stated earlier. I attached screenshot below for your reference. 

Best regards,

hlseck

[ZiYing_Intel]

Hi hlseck,

If you see the Qsys Path error message carefully, you untick below parameters and you will find that your issue resolved.

Best regards,

Zi Ying

[ZiYing_Intel]

Hi hlseck,

I believed that I answered your question, I am now close the case.

If you have any question after the case closed, please do feel free to submit another issue. There will have people reach out to you.

Best regards,

Zi Ying

[hon1]

Dear ZiYing,

I cannot see the image you attached. Could you do it again?

Best regards,

hlseck