FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
5690 Discussions

Problem with Cyclone V GX Pin No AB11 and AB10


I am using my custom board having cyclone 5CGXFC9C6F23I7N devce along with other Chips like GS82582QT19GE-400I and marvel PHY 88E1111 , i have Third party MAC also on board.


Case:1 i am able to communicate on network with my MAC along with marvel PHY they both works fine able to ping on network send and receive data independently . (Give 125Mhz Clock from independent source)

Case: 2 i am able to Write and read data on GSI memory without any issue , this memory required two clock (CLK+ & CLK-) for its operation , i assign CLK+ to pin no AB11 and CLK- to pin no AB10 of cyclone device. here i give +ve and -ve 33Mhz Clock from independent source through pll.


Problem When i Combine both (Case 1 & Case 2) , the my Network section (case: 1) stop working , if i remove memory clock assignment

( CLK+ @ PIN No AB11) and CLK- @PIN No AB10), it start working again.

Observation 1: If i completely remove all memory assignment from board (Data, address control etc) and also remove memory control block (RTL Block) etc and left only clocks which come directly from PLL it also stop working.


Observation 2: i have another board having cyclone V GX Device without any memory on board and i found there is no such issue. i mean board able to communicate on network and assigning CLK+ to AB11 and CLK- to AB10 will not affect the functionality of network.


please suggest what went wrong or missing ? or how i overcome this problem.


0 Kudos
1 Reply

Just basing on your description. My guess is it could be a signal integrity or power integrity issue, im not sure which. it could be the clock activates the memory, and it starts consuming more power or generating noise which interrupted the network traffic. 


0 Kudos