Problem with the clock of the 10M08SCE144

[PedroJServian]

Good morning, colleagues,

I'm designing an FPGA to make a dead time and minimum pulse program for PWM signals coming from a uC. I performed a testbench of the design of these entities and they worked fine. The problem I saw when loading the design in the FPGA is that I saw that the dead time and minimum pulse times were increasing. It seemed strange to me that they increased and also with the same ratio. I have taken the signal from the CLK that I put in the modules and I have seen that the clock signal instead of being 116MHz as indicated in the datasheet and in the PLL, is 82-85MHz. To check the 82-85MHz signal I have taken the signal through PIN 89 and I have checked it in the oscilloscope. What I would like to know is why I don't pull out the 116MHz clock and pull out one of approximately 84MHz.

I would also like to know why the clock appears as a sinusoidal if I am not applying any filter on the oscilloscope or on the board. I thought it should come out as a square wave. I got the clock generator from “Internal Oscillator” in the “Configuration and Programming” section of “Basic Functions”.
Anyway, I would like to know how to use a 116MHz or programmable clock with the library you offer.

I expect your answer. Have a nice day.

BR,

Pedro

[Farabi]

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[FvM · Accepted solution]

Hi,

internal oscillator has an only roughly defined frequency, datasheet says min. 55, typ. 82, max. 116 MHz. Measured 84 MHz corresponds nicely to typical value. Specifying a different value in component instantiation has no effects on hardware, only in simulation.

To understand why you see sine waveform on oscilloscope, we need to know about IO standard and probing details. Unloaded pin waveform is basically a square wave, I guess you have low drive strength (e.g. 2 mA) and high load capacitance, e.g. 1:1 passive probe or direct connected coax cable.

[PedroJServian]

Thanks!!. Another question I would like to know. As the internal oscillator is 84-85MHz, I guess that it's the maximum speed of a clock we can have, isn't it? In order to design the counters in some vhdl designs.

Have a nice day,

Pedro

[FvM]

Hi,
maximal MAX10 core clock is in the 400 MHz range, maximal frequency of input signals depending on the performance of used IO standard. It's expected that you have a stable clock source, e.g. crystal oscillator for the FPGA, high frequency internal clocks are often generated with the help of PLL. Internal oscillator is intended for purposes that don't need precise timing, e.g. loading FPGA configuration. Due to frequency tolerance and relative large jitter of internal oscillator, you don't see applications that feed FPGA PLL from internal oscillator although this might work.

[Farabi]

Hello,

It is not recommended to use internal oscillator if you design requires accuracy timing. You can use PLL instead feed by external clock oscillator. This is more reliable.

regards,

Farabi