Problems Rebuilding Golden Reference Design on Cyclone V SoC Development Kit

[Altera_Forum]

Hello. I'm new, here, and starting work with the Cyclone V SoC Development Kit. While things seem to be working, I like to rebuild the design(s) that ship with the boards so be sure I have a working base to start my research into flow and development. Seems this is a logical place to start (feel free to suggest otherwise). 

 So I installed Quartus II 14.0sp2 as I have the REV E board and also got the accompanying BSP downloaded from Altera. I'm able to use this to program the FPGA and do some basic things, but when I try to build the "Golden System Ref Design" I have problems. I've poked around Rocketboards.org with no luck resolving this.  My major issue is that when I bring up Qsys, and have to reassign base addresses, for some reason, I can finally get to generate but then I see this:  ... Info: rsp_mux: "mm_interconnect_2" instantiated altera_merlin_multiplexer "rsp_mux" Info: Reusing file C:/altera/14.0sp2/kits/cycloneVSX_5csxfc6df31_soc/examples/golden_system_ref_design/hardware/cv_soc_devkit_ghrd/soc_system/synthesis/submodules/altera_merlin_arbitrator.sv Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Error during execution of "{C:/altera/14.0/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Execution of command "{C:/altera/14.0/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed Error: border: Error during execution of script generate_hps_sdram.tcl: seq: child process exited abnormally Error: border: Error during execution of script generate_hps_sdram.tcl: Generation stopped, 3 or more modules remaining Error: border: Execution of script generate_hps_sdram.tcl failed Error: border: 2015.07.15.09:16:24 Warning: Ignored parameter assignment extended_family_support=true Error: border: 2015.07.15.09:16:24 Warning: Ignored parameter assignment device=5CSXFC6D6F31C6 Error: border: 2015.07.15.09:16:30 Warning: hps_sdram: 'Quick' simulation modes are NOT timing accurate. Some simulation memory models may issue warnings or errors Error: border: 2015.07.15.09:16:30 Info: hps_sdram: ECC will be enabled in the preloader because an interface width of 24 or 40 has been chosen. Error: border: 2015.07.15.09:16:30 Warning: hps_sdram.seq: This module has no ports or interfaces Error: border: 2015.07.15.09:16:30 Warning: hps_sdram.p0: p0.avl must be connected to an Avalon-MM master Error: border: 2015.07.15.09:16:30 Warning: hps_sdram.p0: p0.scc must be exported, or connected to a matching conduit. Error: border: 2015.07.15.09:16:30 Warning: hps_sdram.as: as.afi_init_cal_req must be exported, or connected to a matching conduit. Error: border: 2015.07.15.09:16:30 Warning: hps_sdram.as: as.tracking must be exported, or connected to a matching conduit. Error: border: 2015.07.15.09:16:30 Warning: hps_sdram.c0: c0.status must be exported, or connected to a matching conduit. Error: border: 2015.07.15.09:16:31 Info: hps_sdram: Generating altera_mem_if_hps_emif "hps_sdram" for QUARTUS_SYNTH Error: border: 2015.07.15.09:16:33 Info: pll: "hps_sdram" instantiated altera_mem_if_hps_pll "pll" Error: border: 2015.07.15.09:16:33 Info: p0: Generating clock pair generator Error: border: 2015.07.15.09:16:34 Info: p0: Generating hps_sdram_p0_altdqdqs Error: border: 2015.07.15.09:16:40 Info: p0: Error: border: 2015.07.15.09:16:40 Info: p0: ***************************** Error: border: 2015.07.15.09:16:40 Info: p0: Error: border: 2015.07.15.09:16:40 Info: p0: Remember to run the hps_sdram_p0_pin_assignments.tcl Error: border: 2015.07.15.09:16:40 Info: p0: script after running Synthesis and before Fitting. Error: border: 2015.07.15.09:16:40 Info: p0: Error: border: 2015.07.15.09:16:40 Info: p0: ***************************** Error: border: 2015.07.15.09:16:40 Info: p0: Error: border: 2015.07.15.09:16:40 Info: p0: "hps_sdram" instantiated altera_mem_if_ddr3_hard_phy_core "p0" Error: border: 2015.07.15.09:16:41 Error: seq: Error during execution of "{C:/altera/14.0/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally Error: border: 2015.07.15.09:16:41 Error: seq: Execution of command "{C:/altera/14.0/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed Error: border: 2015.07.15.09:16:41 Error: seq: child process exited abnormally Error: border: 2015.07.15.09:16:41 Info: seq: "hps_sdram" instantiated altera_mem_if_hhp_ddr3_qseq "seq" Error: border: 2015.07.15.09:16:41 Error: Generation stopped, 3 or more modules remaining Error: border: 2015.07.15.09:16:41 Info: hps_sdram: Done "hps_sdram" with 7 modules, 33 files Info: border: "hps_io" instantiated altera_interface_generator "border" Info: soc_system: Done "soc_system" with 65 modules, 123 files Error: ip-generate failed with exit code 1: 34 Errors, 4 Warnings Info: Finished: Create HDL design files for synthesis   I don't get what is really failing, here. I can't find any references to what these errors (the first one, especially) refers to. I've checked that I have the most recent cores and versions of things. Any other ideas? I'd really like to rebuild this, program the board and see it work as it does from the factory boot. Then I have something to start with.  Also, it seems that the BSP kit is missing some pretty basic things, in my opinion. Anyone have any solutions/suggestions on how to get the following items:  1) A proper pin description file for which FPGA pins are connected to what hardware on the board (with pin types, also) - seems the golden top project doesn't have this! Seems like it should...  2) Source code for the custom program(s) supplied in the boot image (not standard Linux source, per se, but the custom work done to make it work with the hardware installed). 3) Source Quartus project files for the board test system - this would be huge as it would, I think, give us everything we need to put our own designs into the development kit without doing so much busy-work to get pin-outs right, interfaces right, etc.  Sorry for all the noob questions, but I didn't see much on these when I searched/Googled.  Thanks!

[Altera_Forum]

maybe is time to reinstall the 15.0 and retry again?

[Altera_Forum]

You really should *never* choose a custom install path for Quartus. You appear to have installed it in "C:/altera/14.0sp2/" when the default path is "C:/altera/14.0/". If you notice the error message from Qsys, it is looking in the latter directory. 

 Did you install the 14.0.2 patch in a custom directory? (note it is not 14.0 SP2, it's 14.0.2!) If so, uninstall the patch and then reinstall it in the *default* directory, 14.0/

[Altera_Forum]

oh yeah...TVworld is right.. the quartus II got a lot of hard coded path during compilation...and currently as i know it is not dynamically locate custom installation folder... maybe go try 15.0 and do not change any of the folder name during installation.