Hi,I used the Nios II EDS sof2flash program in the Quartus II 9.1 License Edition to convert a sof file to flash format. I attempted to use the Board Update Portal and the Nios II EDS to program the flash memory with the flash file on my Stratix IV GX FPGA development board (device EP4SGX230KF40C2N). After the file loads 100% successfully into the flash memory, I turn the rotary switch (SW2) on the board from position 0 to 1, then power cycle the board, but an error occurs and red LED D27 comes on. I tried again to program the flash memory and when complete, I pressed the CONFIGN button (S1), but I still get the same error. By the way, the sof file is targeted to my specific device and the Mega Cores used in this sof file are all fully licensed. But we noticed that the size of the flash file created by Nios II EDS is 28 MB and the User Hardware portion of the flash memory is only 12MB. Looks like we're getting this error because I'm trying to make fit a flash file that's too large for the allotted memory space? How do I reduce the size flash file created by Nios II? Thanks, Eric ------------------------------------------------------- Electronics Engineer Microwave and Communication Systems Branch NASA Goddard Space Flight Center, Code 567 8800 Greenbelt Road, Greenbelt, Maryland 20771, USA Building 25, Room S054, Mail Code 567.3 Phone: (301)-286-3439 Email: firstname.lastname@example.org -------------------------------------------------------
I have the same problem with the StratixIV GX Development Board and QuartusII 9.1. While trying to do the board recovery process, I discovered that there is an errata in the file "altera\91\kits\stratixIVGX_4sgx230_fpga\factory_recovery\build_factory_source\build_factory_readme.txt". It says:Problem Description: The release of Nios II EDS 9.1 tool "sof2flash" does not include support for Stratix IV GX . Work-around: ..... The described the procedure, but the 9.1.0 kit that I have does not have the required file "s4gx230_pfl_programming.sof" required to do parallel programming. I submitted an SR and the response confirmed that this is a bug in 9.1. I have updated my SR to request the "s4gx230_pfl_programming.sof" file. With respect to the .flash file size, the .flash file is in the SREC format which has a text based representation of the binary image. My experience is that this will be over twice as large as the actual binary image.
I had the same issue with Arria II GX development board and Quartus II 9.1 software. It looks like there is an issue with 9.1 software. Try using 9.0 SP2 it might work. If you want to load a new design try this procedure:1. Program the FPGA with the PFL program that comes with the dev kit. Since I am using Arria II GX my factory default SOF file is located in C:\altera\90\kits\arriaIIGX_2agx125es_fpga\factory _recovery\build_factory_source\a2gx_pfl_programmin g.sof. I am hoping you will have a similar file for Stratix IV dev kit after you install the kit installation from the following website http://www.altera.com/products/devki...it-siv-gx.html (http://www.altera.com/products/devkits/altera/kit-siv-gx.html). 2. Create the POF file for the flash using Quartus 9.0 SP2, as 9.1 did not work for me. Use the COF in the same directory that is mentioned in step 1 for creating the POF file. Update only the user SOF file and leave the factory default SOF file. 3. Open Quartus programmer. Click the auto detect button which will show the complete chain. Right click on CFI_<SIZE> and change file to the POF that was created in step 2. Program the USER page(in my case it is page 1, and I think it will be the same for you) of the flash only and do a power cycle. You program will be loaded in the user space of the flash. 4. You might need to move some switch in the board to a particular position to load the user code. Refer to the reference manual of the card for more help on the switch. Hope this helps.
Hi Jake,I have mentioned about this issue to an Arrow FAE and he has sent a request to Altera. Hopefully Altera will fix this issue in their next service pack. Kumaran
If you just want to download your sof into flash, just use Quartus programmer rather than using sof2flash and nios2-flash-programmer. Those program does have issue in 9.1Just create PFL only FPGA design and download via FPGA. I think the sof area for user is 0x00C20000, don't forget to set the PFL option bit set to 0x18000
--- Quote Start --- Well truly it looks like the thing to do is to get Altera to fix it. Let me call some people. Jake --- Quote End --- Thanks Jake and Kumaran. I have submitted an Altera service request 10742901. Nekojitu, I'm working on this now! Thanks, Eric
I will try and fix it myself tomorrow. However, here is response from Altera's NIOS II specialist:--- Quote Start --- It looks like this is all resolved in SP1 ( not sure exactly when that is coming out but it is soon. I will let you know when I find out. ) If you need it before sp1 there are 2 patches you can request by filing an SR Again, it's patch 0.63 and patch 0.73. --- Quote End --- Jake
Oh I should clarify. One of these patches fixes the problem with generating compressed files for Cyclone III. The other deals with the sof2flash support for Stratix IV GX.Jake
Hi Jake,Thanks for the solution. I also had another issue with 9.1 not able to generate a POF file for the flash. The error(actually an info message) message that I get with 9.1 is "Size of file(s) in CFI_512MB exceeds memory capacity" and then another message saying it failed to generated POF file. I used the COF file that was provided by Altera. But, with the same COF file I can get it to work with 9.0 SP2. I am using Arria II GX dev board and not Startix IV. I will try to get the patch that you have mentioned and see if the POF file generation issue is resolved as well. Kumaran
HiWe have the same problem as described in original post by Eric Harris - unable to program working design into Stratix IV GX FPGA Development Kit via web portal. We tried to convert with sof2flash from QuartusII 9.0 SP2 as well as QuartusII 9.1 - it makes no difference. So the questions except the obvious "what's the easiest way to make things work?" are: 1. Should we check on "compressed bitstream" checkbox on setting/Device&Pins Options/Configuratiob tab or better keep it unchecked? 2. Does Development Kit in question support the "Parallel Flash Loader" described in AN386 or the "FPGA-Based Parallel Flash Loader" described in AN478? Or both? Or neither? 3. If it supports PFL from AN386 then where exactly should we specify the address of the user hardware image in the flash memory (0x2c0000)? Convert programming files dialog doesn't get me to change the address of the sof. 4. If it supports PFL from AN478 then I'd like to get precompiled image of FPGA with PFL. Or, at least the ready-made project that I could easily compile. Now rant on. 5. Why the user guide so f****ing unusable when it comes to flash programming methods others than BUP? 6. How 9.1 was shipped with such an obvious bug? Nobody in Altera's QA never attempted to burn a user image into the flash with the only method officially recommended in the user guide? 7. Why the problem is not documented in the latest release notes? 8. Why patch 73 is not available for free download on Altera web site?
1. check the MSEL pin. It should not use compressed.2. It supports both. PFL in MAX2 device is used to load FPGA data out from Flash where as FPGA base PFL will be allow you to write FPGA data into Flash 3. The option bit address is 0x18000, first page of FPGA data should be 0x20000, second page should be 0xC20000. You should be able to change address for each page, it will be written as option bit.
--- Quote Start --- 1. check the MSEL pin. It should not use compressed. --- Quote End --- I don't understand what you are talking about. There is no checkbox called "MSEL pin" on Setting/Device&Pins Options/Configuratiob tab. --- Quote Start --- 2. It supports both. PFL in MAX2 device is used to load FPGA data out from Flash where as FPGA base PFL will be allow you to write FPGA data into Flash --- Quote End --- According to AN 386: --- Quote Start --- The Max II PFL feature has the following functions: ■ Programming the CFI flash device through the MAX II JTAG interface. ■ Controlling Altera FPGA configuration from a CFI flash for ACEX® 1K, APEX™ 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria® series, Cyclone® series, FLEX® 10K (FLEX 10KE and FLEX 10KA), Mercury™, and Stratix® series FPGA devices. --- Quote End --- It seems to me, default MaxII on Stratix IV GX devkit only capable of the second part - controlling Altera FPGA configuration. At least for me, programming CFI flash with MAX II doesn't work at all. --- Quote Start --- 3. The option bit address is 0x18000, first page of FPGA data should be 0x20000, second page should be 0xC20000. You should be able to change address for each page, it will be written as option bit. --- Quote End --- You forgot to mention that in order to be capable to modify the address one should change "Address mode for selected pages" from "Auto" to "Start". Anyway, thanks Altera, I wasted another couple of hours. Now trying to solve it with PFL from AN478.
MSEL is a FPGA pin which determine if you can use compress mode or notAs I mentioned, the PFL in max2 on this board only supports loading data, and PFL in FPGA on this board only supports write Flash function. It is just a matter of what external chip can do and what already implemented in the max2. If you change max2 PFL, sure you can write into Flash. So AN386 is still correct. Yes, you need to set start or block, otherwise, auto will set start/end (most likely, start from 0x00 and the next page to be right after the previous page)
O.k. The combination of Stratix-IV-based flash programmer (as in AN 478) with MAX2-based fpga loader (as in AN 386) appears to work.Still, it took way too much time and effort. IMHO, somebody from Altera support organization has to write step-by-step description of the process. In particular, for a person that has no intimate knowledge of PFL it is not at all obvious that OPTION bits should not be programmed into the flash. Also pre-build SOF image containing properly instantiated PFL module should be made available on Altera web site as well as included in distribution package of the dev. kit (preferable in zip form rather than in .exe and/or .qar form, because it should be usable on machine that has no Quartus installed by person that has no administrator/power_user privilege).
If you have Quartus II 9.1 SP1 installed, you no longer need to program the device first and then read it back as .flash file.To convert a .sof to a .flash file, use the following command in Quartus II 9.1 SP1: sof2flash --pfl --optionbit=<option bit address offset> --input=<your SOF.sof> --output=<output.flash> --offset=<desired image offset> For example, to create a .flash file for the Stratix IV GX Development kit sof2flash --input=<yourfile>.sof --output=<yourfile>.flash --offset=0xC20000 --pfl --optionbit=0x18000 Output: • A FLASH file containing the SOF data. • A FLASH file containing single image option bits for the PFL located at the address you specified with the --optionbit=<offset> option. You should only program the *.map.flash file to flash if either of the following applies: 1. You don't have existing option bits at the appropriate location in flash 2. You only need to configure a single image. Note that most of the Altera development board should already have the option bits, so there is no need to program the *.map.flash
Thank you, sirene. BUP works now.Out of curiously, why do we need this new --pfl flag? I was under impression that PFL programming data stream is exactly the same as [uncompressed] passive serial which is supposedly a default for sof2flash. However the fact is - on S4-GX devkit without new flag PFL doesn't work. Where is a catch? Another question. Why is sof2flash so damn slow? I already figured out that Altera tools programmer, especially those from the assembler, sopcbuilder and Nios sides, value their time well above their customers time so they code in perl, tcl or at best in java what for the customer's benefit should be coded in C/C++. However in case of 'sof2flash --pfl' the slowness was taken to a new extreme and now, instead of being just annoying, it really disturbs the development process.
Hi MSHATZ,I don't think I have good answers for you this time, but I think somewhere in the development kit collateral it says that sof2flash in 9.1 does not support Stratix IV GX. I guess in order to support it, they have to create a new --pfl option just to indicate that this is for PFL and there'll possible be multiple sof files in the flash. Also not sure why the sof2flash is slow, possibly due to the sheer size of the programming file (considering Stratix IV GX is a big device?) I'm not sure though, but if you have some comparison, you should probably report it back to Altera. Thanks.