Problems with altera_reserved_tck

[Altera_Forum]

I have a Nios II system with level 1 JTAG debug module and I'm having alot of problems with altera_reserved_tck. I've included the sdc constraints for the JTAG module suggested by the time quest cookbook below, 

 create_clock -period 10MHz {altera_reserved_tck} set_clock_groups -asynchronous -group {altera_reserved_tck} set_input_delay -clock {altera_reserved_tck} 20 [get_ports altera_reserved_tdi] set_input_delay -clock {altera_reserved_tck} 20 [get_ports altera_reserved_tms] set_output_delay -clock {altera_reserved_tck} 20 [get_ports altera_reserved_tdo]   When compiling the design, I'm constantly receiving negative removal slacks involving altera_reserved_tck. I'm very unsure how to correct this. Since this problem has developed, I'm unable to run code, as the Nios II IDE fails on program memory verify, or starts doing unusual things.   Has anyone had a similar problem or can make suggestions? If you require design files I'm not sure how I could send them to you?

[Altera_Forum]

I have the same trouble. 

I'm using a DK-DSP-3C120N kit.Recently,I'm struggling with the DDR2 HP Controller under the direction of AN517(Using High-Performance DDR, DDR2, and DDR3 SDRAM With SOPC Builder).The design is targeted to the Cyclone® III EP3C120F780C7 Kit.  In this example,the SOPC system contain a Half-Rate DDR2 Controller working at 150MHz(altmemddr_auxfull),the PLL of the controller simultaneously generate a 75MHz output clock(altmemddr_sysclk) which been used as SOPC system clock.  After compilation,I got three critical warning,cause by JTAG.The TimeQuest report negative slack(-2.435) in Summary(Removal) of altera_reserved_tck. The Top Failing Paths (Removal:altera_reserved_tck) is this: Slack:-2.435 From---altera_reserved_tck  To-----pzdyqx:nabboc|pzdyqx_impl:zdyqx_impl_inst|FNUJ6967  I've tried to slow the DDR2 clock down to 133.333MHz,the NIOS clock down to 66.667MHz,but the slack value still negative.  I lose my head of this because I've constrained the JTAG using the templet:# JTAG Signal Constraints constrain the TCK port create_clock -name tck -period 100.000 [get_ports altera_reserved_tck]# Cut all paths to and from tck set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck]# Constrain the TDI port set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdi]# Constrain the TMS port set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tms]# Constrain the TDO port set_output_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdo]  Can anybody help us? Thank you very much!

[Altera_Forum]

Just an ignorant question: Are there any indications, that the JTAG interface actually needs timing constraints? In my opinion, it's effectively impossible to create timing violations with the 6 MHz USB Blaster TCK, unless adding inappropriate clock buffers or simiar.

[Altera_Forum]

I read advice under a different thread about something similar, which was to ignore this warning. Usually tracking down and removing warnings is a good thing, but not in this case. I thought that the problem I was experiencing might be related to this warning, but is wasn't. So I suggest that you just ignore it. Hope this helps.

[Altera_Forum]

Time constraints applied to altera_reserved_tck haven't helped me to fix this problem. 

 In my case the problem solution was quite simple. After to added a constraint to NIOS clock signal, all my jtag errors (related with clock altera_reserved_tck) disappeared. Eg   --- Quote Start ---  # Clock constraints create_clock -name "MCLOCK" -period 20ns [get_ports {NIOS_CLK}] -waveform {0.000ns 10.000ns}# Automatically calculate clock uncertainty to jitter and other effects. derive_clock_uncertainty  --- Quote End ---    where NIOS_CLK is the pin name related with oscillator input.  BR,