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Altera_Forum
Honored Contributor I
767 Views

Program CPLD from Cyclone IV on BeMicro board

Hi all, 

 

This one's probably pretty basic, but I can't seem to find the answer anywhere... 

 

I want to program a MAX V CPLD _through_ the Cyclone IV on the BeMicro SDK board. On a ground-up design you would insert the CPLD in the JTAG chain with the FPGA, but I don't want to hack the BeMicro hardware, and don't see a way to do this without some creative soldering. (?) 

 

So what I want to try is hooking the CPLD JTAG lines to the FPGA's GPIO lines. 

 

PC <--JTAG--> FPGA <--GPIO--/--JTAG--> CPLD 

 

But it's unclear what to instantiate within the FPGA to make the connection... if I had access to the JTAG lines, it would be pretty simple... Can this be accomplished with the Virtual JTAG or other JTAG-related megafunction? Is the whole idea misguided? 

 

Thanks much, 

Don
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4 Replies
Altera_Forum
Honored Contributor I
50 Views

You can connect the GPIO-JTAG pins to virtual JTAG, but the Quartus programmer won't support it as programming target. You need to write your own JTAG programming design, similar to embedded Jrunner and write configuration files to it.

Altera_Forum
Honored Contributor I
50 Views

Thanks for the quick reply! Just to clarify, in your suggested solution, the Jrunner-like software runs on the PC, talking to the virtual JTAG such that it effectively programs the CPLD, right? 

 

What about porting Jrunner to run on the NIOS, strapping it directly through the appropriate GPIOs? This eliminates the need for the virtual JTAG, right? Though of course it means you have to get the programming files over to the NIOS somehow... 

http://www.alterawiki.com/wiki/nios_jrunner_example 

 

Or, third option: that hardware hacking is sounding better and better... 

 

Thanks for the help, 

Don
Altera_Forum
Honored Contributor I
50 Views

Huh, Jrunner doesn't appear to support MAX CPLDs. There must be an open source MAX V programmer out there that could be ported to NIOS.... Is this a sound approach?

Altera_Forum
Honored Contributor I
50 Views

Hi Don, 

 

--- Quote Start ---  

 

I want to program a MAX V CPLD _through_ the Cyclone IV on the BeMicro SDK board. On a ground-up design you would insert the CPLD in the JTAG chain with the FPGA, but I don't want to hack the BeMicro hardware, and don't see a way to do this without some creative soldering. (?) 

 

So what I want to try is hooking the CPLD JTAG lines to the FPGA's GPIO lines. 

 

PC <--JTAG--> FPGA <--GPIO--/--JTAG--> CPLD 

 

But it's unclear what to instantiate within the FPGA to make the connection... if I had access to the JTAG lines, it would be pretty simple... Can this be accomplished with the Virtual JTAG or other JTAG-related megafunction? Is the whole idea misguided? 

 

--- Quote End ---  

The Virtual JTAG interface can be used for the communication from the host component of this design, but unfortunately Quartus will not recognize this sequence of hardware as a JTAG chain, so you won't see your device in the programmer. 

 

I have used the Jam STAPL programmer to implement this type of interface. Basically you provide toggle callbacks for TCK/TMS/TDI/TDO. In this scheme you would have a Virtual JTAG or JTAG-to-Avalon-MM bridge component in your BeMicro and treat it like a GPIO board. 

 

You could buy a Terasic USB-Blaster for $50. 

 

Or if you are up for a challenge, you can buy the BEMICRO-PROTO board, an FTDI FT245R module (UM245R), solder that to a header on the BEMICRO-PROTO board, and then build your own USB-Blaster logic in the BeMicro (and the FT245 EEPROM) ... for probably around $50 plus your time. 

 

Cheers, 

Dave
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