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Programming CycloneV FPGA from U-Boot SPL

JFrye2
Novice
905 Views

I have a DE1-SoC board from Terasic. I am trying to boot a Linux kernel that can talk to the hardware in the FPGA portion. I am trying to verify that my FPGA is programmed during the boot cycle. I am currently following this workflow.

https://rocketboards.org/foswiki/Documentation/BuildingBootloader

My bootlogs show no indication that the FPGA is being programmed by the preloader before the kernel is decompressed and started.

U-Boot SPL 2019.04-00246-g0c3e6f623d-dirty (Dec 20 2019 - 22:19:44 -0500)   Trying to boot from MMC1           U-Boot 2019.04-00246-g0c3e6f623d-dirty (Dec 20 2019 - 22:19:44 -0500)       CPU:  Altera SoCFPGA Platform   FPGA: Altera Cyclone V, SE/A5 or SX/C5 or ST/D5, version 0x0   BOOT: SD/MMC Internal Transceiver (3.0V)       Watchdog enabled   DRAM: 1 GiB   MMC:  dwmmc0@ff704000: 0   Loading Environment from MMC... *** Warning - bad CRC, using default environment       In:  serial   Out:  serial   Err:  serial   Model: Altera SOCFPGA Cyclone V SoC Development Kit   Net:   Warning: ethernet@ff702000 (eth0) using random MAC address - a2:77:81:44:49:7a   eth0: ethernet@ff702000   Hit any key to stop autoboot: 0   switch to partitions #0, OK   mmc0 is current device   Scanning mmc 0:1...   Found /extlinux/extlinux.conf   Retrieving file: /extlinux/extlinux.conf   157 bytes read in 1 ms (153.3 KiB/s)   1:   Linux Default   Retrieving file: /extlinux/../zImage   4700440 bytes read in 241 ms (18.6 MiB/s)   append: root=/dev/mmcblk0p2 rw rootwait earlyprintk console=ttyS0,115200n8   Retrieving file: /extlinux/../socfpga_cyclone5_socdk.dtb   28016 bytes read in 3 ms (8.9 MiB/s)   ## Flattened Device Tree blob at 02000000     Booting using the fdt blob at 0x2000000     Loading Device Tree to 03ff6000, end 03fffd6f ... OK       Starting kernel ...

When I start readinng fpga_manager sysfs files, they suggest the FPGA is not powered on

root@cyclone5:~# cat /sys/class/fpga_manager/fpga0/state power off

Does anyone know how to verify that the FPGA is programmed by the bootloader and if not, then how to program it with the bootloader

 

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6 Replies
Fawaz_J_Intel
Employee
661 Views

Hello,

You should be able to read a message by uboot saying that it has read your rbf file loaded successfully.

 

## Executing script at 02000000

reading system.rbf

3088784 bytes read in 163 ms (18.1 MiB/s)

 

 

You can also view your devices on FPGA side from linux, if they are not available, it means it was not configured.

 

cat /sys/class/fpga_manager/fpga0/state

 

If you see the output "operating" then your FPGA is configured.

 

I use a script to load the FPGA image boot.scr, you can use it and test your system. You need to set the rbf name to system.rbf and the device tree file to socfpga.dtb.

 

 

Thank you

 

Fawaz_J_Intel
Employee
661 Views
posted a file.
JFrye2
Novice
661 Views

Can you also attach the uncompiled version of the script with the command you used to compile it? Thanks.

More information on this forum as well: https://forum.rocketboards.org/t/cyclonev-programming-fpga-from-u-boot/2230/7

JFrye2
Novice
661 Views

Firstly, should that FPGA programming message come up with the default version of uboot on github right now? Does the bsp-create-settings command grab the rbf and build it into u-boot with commands to program the FPGA or does this need to be added manually?

How do you partition and pack your files on to the SD card? Do you need to point u-boot to your script or will it begin running it automatically?

I was using this script https://raw.githubusercontent.com/rsarwar87/altera-soc-rootfs/master/make_sdimage2.py to simplify the partitioning/formatting process. This script will only let you make 4 partitions it seems each with only one file per partition. Is there a way to combine the u-boot-with-spl.sfp with the uboot.scr into one binary?

Thanks,

Fawaz_J_Intel
Employee
661 Views

Hello,

We cannot combine uboot with rbf file for Cyclone V SoC devices.

The rbf file should be available inside the FAT partition. After that, you can load this rbf file from uboot and uboot will configure the FPGA for you. The scr script is needed to automate uboot commands.

We recommend to use the uboot from this link:

http://github.com/altera-opensource/u-boot-socfpga

 

 

Thank you

thanhtung
Beginner
443 Views

hi @JFrye2
I'm following the same guide and De1-SoC as you. But after I create img and use putty boot it on board, nothing happens like the below photo. So could you tell me Did you do anything other than what is in the guide? And what value of MSEL did you use? that is [00000] or [01010]?

Thank you so much!

 
 
 
 
 
 
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