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FPGA Evaluation and Development Kits

Programming .JIC Trouble

Altera_Forum
Honored Contributor II
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Hi, I have read and followed the directions out the user manual for the DE0-nano for programming the EPCS64 spansion memory and generated the .jic file fine from my .sof file. The problem lies when I try to program the file via the programmer window it reaches 0% and fails when just the .jic file is selected. I can program the .sof file just fine on the device, but cannot see why the .jic file fails. I have tried erasing the device as well and that fails right away also. Any suggestions will be very helpful. Is there a log file I can view or something?

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Altera_Forum
Honored Contributor II
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I think I also might have been trying to load my compiled design file .sof and the .jic file at the same time so the factory default enhanced SFL image was never loading. I deleted the .sof file from the programmer window and just loaded the .jic file and I got it working. My mistake.

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