I have a Cyc V GI PCIE board. I can run the web based example as documentedin the user guide (ug_cvgt_fpga_dev_kit.pdf). Using this GUI, you can change
the clock frequency of X3 and X4. These are controlled through the CPLD on the board. There does not appear to be any source code for the FPGAs factory build. None of the documentation has any details or examples of how these clocks are
controlled. If there is no example HDL, how do we use these clocks in our designs, or do anything else with this board except start from scratch. Am I missing something, like a whole directory of files?
Currently I am reviewing the forum for any open questions and found this thread. I apologize that no one seems to answer this question that you posted. Since it has been a while you posted this question, I'm wondering if you have found the answer? If not, please let me know, I will try to assign/find someone to assist you. Thank you.
Nooraini, Thanks for picking this up, I have not gotten any help with this issue. I am wondering if my local FAE could be of some assistance? I am currently shopping for a FPGA board that has a lot of I/O and this one is a perfect match. Cant use it tho without an example design/BSP...
Apology for the late reply, you can download the kit exe from the below link
and you have the code for the Max 5( mention as CPLD) from the below directory structure.
Let me know, if you need further assistance.
Rs, The link you suggest is the home page for the board. On that home page, there are links to download the "installation kit". The windows version will not install because the installshield wizard encounters an error but gives no explanation. I got this to install on a windows 7 system once but this does not install on windows 10. I got the zip file tho, and there is no typical BSP in there. It has the MAX5 contents, a top-level signal def file (goldentop.v), and this project called board update portal which looks like a project to get the board running enough to program the flash?
There are these hsma, hsmb projects but they cannot be opened because qts sez there are errors in the qsf file. None of these projects have any interface to the MAX5 in the source.
Is there a BSP somewhere that I can bring up in qts that has example code for interfacing the MAX5 (and the clocks), or the source for what is in the FPGA when you unpack the kit and connect it up?
What is the purpose of this board if I have to write everything from scratch?
Apology for the windows installation error that happened, I am requesting to install the .exe file as Run as administrator.
When you do the above the installation file will be successfully installed and you can find the bsp code.
RS, I did this and the install script worked. It installed the same content that the .zip does. Can you tell me where in the content that was installed the BSP is? Specifically, I need to see the code that runs on the FPGA when you unpack the board from the factory and run the kits "Clock Control" application. I dont kno for sure which FPGA image should be loaded when you run the Clock Control app.
The MAX5 is apparently being used as an I2C port for the SI clocks. Is there a definition for the registers in the MAX5?
BTW, the demos folder is empty
I went over all of the material in the install. It looks like this is an "open source" distro, lots of code to reverse engineer. So no actual BSP or a template project for quartus.
For those that are thinking about using the Cyclone V GT PCIe board, the SI570 and SI571 programmable clocks are peripherals to the MAX5 PLD. There is a qsys design in the MAX5 that converts a 16-bit parallel I/O control bus to I2C. This PIO bus is the interconnection between the FPGA and the PLD. On the FPGA, the PIO interface is managed through a cfi_flash_atb_bridge component in a qsys project. The software for this project runs uCos2 (missing) and the source project for eclipse is missing. The source code for the app does not have include files with addresses in the MAX5. The addresses on this parallel bus are shared with a parallel flash. The flash addresses are documented in the code, the peripheral addresses are not. There is no documentation on how to use the PLD interface.
If you are looking to use this board for the HSMC interface there are example projects with all the typing done for you. I did not make any of these I dont kno if they work.