FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits

Quad SPI flash IO Voltage

Ms_G
Novice
642 Views

Hi,

 

I am using winbond quad spi flash  - all 4 flash IOs are connected to Cyclone 10 FPGA. 

2 IOs are connected to Bank 1, which is at 2.5VDC level

2 IOs are connected to Bank 8, which is at 3.3VDC level

 

SPI flash device is for Active Serial FPGA configuration and is connected to 3.3VDC.

Is it OK to have flash IOs  in two different DC levels? 

Thanks

 

Labels (1)
0 Kudos
5 Replies
Ms_G
Novice
640 Views

Adding more details

- CS, CLK, DATA0, DATA1 - 2.5 VDC level

- DATA2, DATA3 - 3.3 VDC level

             

0 Kudos
EthanLi
Employee
601 Views

Hi there,


Is your device is Cyclone 10 LP or Cyclone 10 GX?

Since the configuration pin of the Cyclone 10 GX is powered by Vccpgm during configuration, I think your device is Cyclone 10 LP.

For Cyclone 10 LP device, the configuration voltage should be 3.3V or 3.0V based on your MSEL settings.


Please refer to the device handbook 6.3.1. MSEL Pin Settings.

https://www.intel.com/content/www/us/en/docs/programmable/683777/current/msel-pin-settings.html


and the KDB for VCCIO in bank 1:

https://www.intel.com/content/www/us/en/support/programmable/articles/000074744.html


Thanks,

Ethan


0 Kudos
Ms_G
Novice
587 Views

Thanks Ethan for your reply.

Yes its Cyclone 10 LP device. I needed Bank 1 on 2.5VDC as I have true LVDS lines from that Bank.

Can I have voltage level translator 2.5 to 3.3VDC on IO lines to SPI flash? will that work?

Cheers.

0 Kudos
EthanLi
Employee
559 Views

If you use Vccio 2.5V for bank 1 and add a voltage translator between flash and FPGA IO, it would be OK for the hard ware.

But since we do not suggest to configure by this way, I am not sure if there could be any other configuration issue, timing or compile errors.

I suggest to use the 2.5V IOs in the other banks and leave the bank 1 as 3.3V powered.

 

Thanks,

Ethan

0 Kudos
Ms_G
Novice
529 Views

Thank Ethan.

0 Kudos
Reply