FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5277 Discussions

Quartus 10.1 SignalTap II LA "Advanced Trigger Condition" Problem

Altera_Forum
Honored Contributor II
807 Views

Hy everyone ..  

I want to observe the signal from the SDRAM controller. I read/write it from NIOS II. 

I was using the advanced triggered with az_cs , az_rd_n , and az_wr_n for as the triggered signal , but I got this error (*attached picture). 

Does anybody know what is the problem ? 

 

learning source : ftp://ftp.altera.com/up/pub/tutorials/de2/digital_logic/tut_signaltapii_verilogde2.pdf 

 

Thank you in advance, 

Yuyex:o
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
106 Views

I got the problem on the EDGE & Level Detector things..  

I set: 

1. az_cs edge detector = R 

2. az_rd_n egde detector = F 

3. az_wr_n egde detector = F 

 

why there's a problem with that ?? 

 

FYI, I am using SOPC's sdram controller. 

Thank you
Altera_Forum
Honored Contributor II
106 Views

I got the same problem with the edge & level detector. 

I was trying the Tutorial "signaltap ii with vhdl designs (ftp://ftp.altera.com/up/pub/tutorials/de2/digital_logic/tut_signaltapii_vhdlde2.pdf)" but at point 4.2 I get also the "Invalid advanced trigger condition expression" message. Without the edge & level detector the .stp file can be saved without this errormessage. I'm using Quartus II v.10.1 Web Edition. 

 

Is there a solution for this problem?
Reply