- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello
I have quartus prime pro 19.3 version with license in place; i have installed modelsim as part of quartus installation. In order to learn design flow and tool chains within quartus prime pro, i intend to run half adder design and a testbench (https://verilogguide.readthedocs.io/en/latest/verilog/testbench.html). I am able to compile design without any errors . there are a few warnings.
now I want to run testbench and see waveform for function verification.
I have reviewed various blogs and links but i cant find answers i need to figure out how can i run testbench and visualize waveforms.
RTL simulation is very basic capability a designer need
can you help?
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Ankit,
Yes sure, I have seen the link, half adder and the testbench. You can refer to link below for Quick Start Simulation tutorial.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_gs_msa_qii.pdf
Thanks,
Regards
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello,
thanks for the link; but it doesn't help much since it is based on Quartus standard edition Vs i have prime pro edition. the flow breaks from me from starting; pg 4 figure 2; i cant locate those fields and cant make further progress.
thanks
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page